臺灣博碩士論文加值系統

近年來，時空格子碼(space-time trellis code, STTC)的技術被運用於多重輸入多重輸出(multiple-input multiple-output, MIMO)的系統當中。因為時空格子碼不能有效提供多工性，同時也能提供額外的編碼增益。然而其解碼器複雜度遠高於時空區塊碼(space-time block code, STBC)解碼器，因此在硬體的實現上較少人採用STTC編碼。STTC 解碼器的高運算複雜度，主要是因為進行維特比(Viterbi)解碼理論時，需要消耗計算大量的分支(branch)運算。相較於一般用於卷積碼(convolutional code)的Viterbi 解碼器，STTC Viterbi 解碼器需要進行大量的複數(complex-value)運算來計算分支路徑值(branch metric)。比起原本的實數運算，進行複數運算的硬體複雜度更高，也更難設計。除此之外，當原本的單輸入單輸出(single-input single-output, SISO)系統增加為MIMO系統後，Viterbi 解碼過程中的運算量與天線數量以及調變級數(modulation order)成正比。
過於複雜並過高的運算量是STTC 目前尚未被應用在無線通訊規格的主因。 為了改善STTC 難以應用的瓶頸，我們提出了一套低複雜度STTC 解碼理論，利用知名的T-algorighm減少解分支路徑值的運算量以提升STTC 解碼器的硬體可行性，並且利用STTC編碼與硬體設計本身的特質，更可提供精確的SNR估測值。這套解碼理論能根據不同的通道品質，來進行降低複雜度與電力消耗量。我們提出的這項低複雜度STTC 解碼器設計，在0.18μm 的製程下完成晶片實作，晶片將支援QPSK、8PSK 與16QAM 共三種調變，且可運用至4×1以及4×4的MIMO系統中，運作時脈約為15MHz。其吞吐量在QPSK、8PSK 與16QAM調變時，分別為59.2Mbps，33.8Mbps以及15.0Mbps。

Space-time trellis code (STTC) has been widely applied to coded multiple-input multiple-output (MIMO) systems because of its
gains in coding and diversity. However, its great decoding complexity makes it less promising in chip realization compared
to the space-time block code (STBC). The complexity of STTC decoding lies in the branch metric calculation in the Viterbi
algorithm. Compared with the Viterbi decoder for convolutional code, the STTC Viterbi decoder has a large amount of the complex-number
multiplications to calculate the branch metrics. Besides, the amount of the branch metric calculations increases significantly in proportional
with the number of antennas and the modulation order.

The large amount of calculation and complexity design is a major result that STTC code is not applied to the specifications of wireless
communication systems. In order to overcome the bottleneck, we propose an algorithm which reduce the complexity of the Viterbi decoder for STTC.
The proposed Viterbi decoder for STTC apply the well-known algorithm, T-algorithm, to reduce the calculations of branch metric and reduce
the complexity of the hardware design. Beside, the proposed Viterbi decoder uses the characteristics of the STTC code and hardware architecture
to provide accuracy estimated SNR value. The proposed Viterbi decoder reduces the complexity and the power consumption in proportional to
the SNR value. Based on the proposed Viterbi decoder, a reconfigurable MIMO STTC Viterbi decoder is designed and implemented using 0.18 um
technology. The proposed decoder supports the QPSK, 8PSK and 16-QAM modulations with 4×1 and 4×4 MIMO system.
The throughput of the proposed decoder achieves 59.2Mbps, 33.8Mbps, and 15.0Mbps for Q-PSK, 8-PSK, and 16-QAM modulations, respectively.

1 Introduction
2 Space-Time Trellis Codes
2.1 MIMO System
2.2 Channel Model
2.2.1 Rayleigh Fading and Rician Fading
2.2.2 Slow fading and Fast fading
2.3 Generator Sequence
2.3.1 Generator Description
2.3.2 Generator Polynomial Description.
2.3.3 Example
2.4 Performance of STTC codes
3 Space-Time Trellis Code Decoder Algorithm
3.1 Viterbi Algorithm for STTC
3.1.1 Branch Metric Calculation
3.1.2 Add-Compare-Selection
3.1.3 Trace-Back Decoder
3.2 STTC Viterbi Decoder Using T-algorithm
3.2.1 Constant Multiplier Algorithm
ii CONTENTS
3.2.2 Introduction of T-algorithm
3.2.3 Threshold Calculation
3.2.4 Proposed STTC Viterbi Decoder with T-algorithm
3.2.5 Performance Analysis and Simulation Result
3.3 Embedded SNR Estimator
3.3.1 Path Metric Normalization
3.3.2 Embedded SNR Estimator
3.3.3 Adjust Normalization Threshold
3.3.4 SNR-assisted T-algorithm
3.3.5 Performance Analysis and Simulation Result
4 Hardware Architecture
4.1 Proposed Branch Metric Calculator
4.1.1 Candidate Symbol Block
4.1.2 Codeword Calculator
4.1.3 Proposed Gated Clock Branch Metric Calculate Block
4.1.4 Proposed Selected Branch Metric Calculate Block
4.1.5 Branch Metric Calculator
4.2 Proposed Add-Compare-Selector
4.2.1 Embedded SNR Estimator
4.2.2 T-algorithm Controller
4.3 Proposed Trace Back Decoder
4.3.1 Pipeline Trace Back Block
4.4 Simulation Result and Timing Schedule
5 Chip Implementation
5.1 IC Design Flow
5.2 IC Simulation
5.2.1 Synthesis Result
5.2.2 Layout
5.2.3 Post Layout Simulation
5.3 Power Analysis
6 Conclusion

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