臺灣博碩士論文加值系統

本論文提出可供HFC網路上行使用的bursty DQPSK解調器﹐其中burst
timing recovery 採用clock phase correlator﹐此電路優點為
acquisition time短且為minimum jitter。藉著模擬整個HFC網路上行傳
輸﹐可驗證burst timing recovery的功能 ﹐並以FPGA實 際implement
此一bursty DQPSK解調器。最後將看到以商用QPSK chip implement的調
變 解調器﹐已成功結合在cable modem中實際驗證其功能。

In this thesis, we proposed a bursty DQPSK demodulator which can
be used in HFC system uplink. The key component of the
demodulator, burst timing recovery, is implemented as a
clock phase correlator. The advantages of the clock phase
correlator are short acquisition time and minimum jitter. The
function of clock phase correlator was verified in a system
simulation. The demodulator was implemented using FPGA.
Finally, by using commercial QPSK modem chips in an actual
cable modem, we have successfully demonstratedthe modem's
upstream transmission functions.