|  | 
參考文獻[1] Harry Pon , et al. , “Technology Scaling Impact on NOR and NAND Flash Memories and Their Applications” , International Conference on Solid-State and Integrated Circuit Technology , Oct. 2006 , page(s):697-700
 [2] Min She, “semiconductor Flash Memory Scaling” , University of California, Berkeley , Doctor of Philosophy , 2003
 [3] A. Paul, Ch. Sridhar, et al, “Comprehensive Simulation of Program, Erase and
 Retention in Charge Trapping Flash Memories” International Device Electron Meeting ,  2006 , page(s)1-4
 [4]Y. N. Tan, et al. , ” Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer” IEEE Transactions on Electron Device Device,Vol.51 , No.7, 2004, page(s): 1143- 1147
 [5]J. V. Houdt, et al. , ”High-k materials for nonvolatile memory applications”, International Reliability Physics Symposium , April 17-21,2005 , page(s):234-239
 [6]T. Sugizaki, M. Kobayashi, et al. , “Novel Multi-bit SONOS Type Flash Memory using a High-k Charge Trapping Layer” , VLSI Technology Symposium , 2003 , page(s):27-18
 [7]Y. N. Tan, et al., “High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation” ,  International Electron Device Meeting , 2004 , page(s):889-892
 [8]M. S. Joo, et al., ”Dependence of Chemical Composition Ratio on Electrical
 Properties of HfO2 Al2O3 Gate Dielectric” , Japanese Journal of Applied Physics. , No.3A, page(s):1220-1222 , March , 2003
 [9]W.J. Zhu , et al. ”Effect of Al Inclusion in HfO2 on the physical and electrical properties of the dielectrics”, IEEE Electron Devices Letters,Vol.23,NO.11, Page(s):649-651,2002
 [10]G. Molas et al. , “Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications” International Electron Device Meeting , 2007 , page(s):453-456
 [11]Y. N. Tan , “Hafnium Aluminum Oxide as Charge Storage and Blocking-Oxide Layers in SONOS-type Nonvolatile Memory for High-Speed Operation” , IEEE Transactions on Electron Devices , April 2006 , Page(s):654-662
 [12] Z. L. Huo et al. , “Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory” , VLSI Technology Symposium , 2007 , page(s):138-139
 [13]J. Bu, et al., “Retention reliability enhanced SONOS NVSM with scaled programming voltage” , IEEE Aerospace Conference paper , P5-2383 5-2390, 2002
 [14]M. H. White, et al. , “A low voltage SONOS nonvolatile semiconductor memory technology” , IEEE transactions on Components, Packaging, and Manufacturing Technology , June 1997 , page(s):190-195,
 [15]W.J. Tsai, et al., “Data retention behavior of a SONOS type two-bit storage flash memory cell” , International Electron Device Meeting , 2001 , Page(s):32.6.1-32.6.4
 [16]K. T. San , et al. , “Effects of erase source bias on Flash EPROM device reliability” , IEEE Transactions on Electron Devices, V January 1995 , page(s):150-159
 [17]M. Chang et al. , “Charge loss behavior of a metal alumina nitride oxide silicon type flash memory cell with different levels of charge injection” , Applied Physics Letters , 2008 , page(s):232105-232105-3
 [18]G. Verma, et al. , “Reliability Performance of ETOX Based Flash Memory” , International Reliability Physics Symposium , 1998 , page(s):158-166
 [19]S. Haddad, et al. , “Degradation Due to Hole Trapping in Flash memory cells” , IEEE Electron Dev. Letters , 1989 , page(s):117-119
 [20]Y. Shin et al, ”A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs” , International Electron Device Meeting  , 2005 , page(s):327-330
 [21] K.T. Park, et al , “A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond” , VLSI Technology Symposium , 2006, page(s):19-20
 [22] Sandhya C. et al, “Nitride Engineering and the effect of interfaces on charge trap flash performance and reliability” , International Reliability Physics Symposium ,2008 , page(s):406-411
 [23] Z. Huo et al., “Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory”, VLSI Technology Symposium , 2007, page(s):138-139.
 [24]N. Umezawa , et al , “The role of nitrogen incorporation in Hf-based High-k dielectrics : reduction in electron charge traps” , Solid-State Device Research Conference , 2005 , page(s):201-204
 [25]Y.Q. Wang , et al., “Fast erasing and highly reliable MONOS type memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack” , International Electron Device Meeting , 2006 , page(s):1-4
 [26]T.S. Chen , et al., “Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer” Electron Device Letters , 2004 , page(s):205-207
 [27]Gabriel Molas , ”Investigation of Hafnium-aluminum alloys in views of integration an interpoly dielectrics of future Flash memories” , Solid-State Electronics , 2007
 [28] G.Zhang et al. , “Potential Well Engineering by Partial Oxidation of TiN for High-Speed and Low-Voltage Flash Memory with Good 125oC Data Retention and Excellent Endurance” , International Electron Device Meeting , 2009 , page(s):1-4
 [29] P.H. Tsai, Kuei-Shu Chang-Liao et al. , “Charge-Trapping-Type Flash Memory Device With Stacked High-k Charge-Trapping Layer” , Electron Device Letters , July 2009 , page(s):775-777
 [30]ITRS , Process Integration Devices and the structures , 2007 , pp. 35-37
 [31] K. Kim , “Technology for sub-50nm DRAM and NAND Flash manufacturing” , International Electron Device Meeting , 2005 , page(s):333-336
 [32] Y. Park , “Highly Manufacturalbe 32Gb Multi-Level NAND Flash memory  with 0.0098um2 cell size using TANOS(Si-Oxide-Al2O3-TAN) Cell Technology” , International Electron Device Meeting , 2006 , page(s):54-55
 [33] S. Y. Wang et al, “Reliability And Processing Effects Of Band-gap Engineered SONOS (BE-SONOS) Flash Memory”, International Reliability Physics Symposium , 2007, page(s):171-176.
 [34] K. H. Wu et al, “SONOS Device With Tapered Band-gap Nitride Layer”, Electron Device Letters 2005, page(s):987-992.
 [35] H.C. Chien et al., “Two-bit SONOS type Flash using a band engineering in   the nitride layer”, Microelectronics. Eng., 2005, pp. 256
 [36] G. Zhang, “Spatial Distribution of Charge Traps in a SONOS-Type Flash            Memory Using a High-k Trapping Layer”, IEEE Tran. on Electron Device Letters, 2007, page(s):3317-3324
 [37] P.H. Tsai, Kuei-Shu Chang-Liao, et al. , “Novel SONOS-Type Nonvolatile Memory Device with Suitable Band Offset in HfAlO Charge-Trapping Layer” , VLSI Technology Symposium , 2007 , page(s): 1 - 2
 [38] S. Jeon et al. , “High Work-function metal gate and High-k dielectrics for Charge Trap Flash memory device applications” , Solid-State Device Research Conference ,  December 2005 , page(s):325-328
 [39] S. Jeon et al., “Impact of metal work function on memory properties of Charge-Trap-Flash devices using Fowler–Nordheim P/E Mode” , Electron Device Letters , June 2006 , page(s):486-488
 [40] Antonio Arreghini , et al., “Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells” , IEEE Transactions on Electron Devices , May 2008 , page(s):1211-1219
 [41] N. Goel , et al. , “Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer” , Electron Device Letters , March 2009 , page(s):216-218
 [42] S. Y. Wang et al, “Reliability and Processing Effects Of Bandgap Engineered SONOS (BE-SONOS) Flash Memory”, International Reliability Physics Symposium, 2007, page(s):171-176
 [43] G.D. Wilk, et al. , “High-K gate dielectrics: Current status and material properties considerations” , Journal of Applied Physic , 2001, page(s): 5243-5275
 [44] K. S. Kim , et al., “Charge Trapping Characteristics of HfO2 Layers for Tunnel-barrier-engineered Nonvolatile Memory Applications” , Journal of the Korean Physical Society , September 2009, page(s):962-965
 [45] R. Singh *, Allen R. Hefner , “Reliability of SiC MOS devices” , Solid-State Electronics , 2004 ,page(s):1717–1720
 [46] G. Zhang et al. ,  “Hot-Electron Capture for CHEI Programming in SONOS-Type Flash Memory Using High-k Trapping Layer” , Transactions on Electron Devices , 2008 , page(s): 1502-1510
 [47] G. Zhang et al. ,  “Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-k Trapping Layer” , Transactions on Electron Devices , 2007, page(s): 3317 - 3324
 
 
 |