跳到主要內容

臺灣博碩士論文加值系統

(216.73.216.167) 您好!臺灣時間:2025/10/31 19:56
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:蔡政育
研究生(外文):Tsai, Cheng-Yu
論文名稱:應用能帶工程電荷儲存層於電荷陷阱式快閃記憶體元件特性之研究
論文名稱(外文):The study of charge trap flash memory device with band engineered trapping layer
指導教授:張廖貴術
指導教授(外文):Chang-Liao, Kuei-Shu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:107
中文關鍵詞:flashband engineeredtrapping layer
相關次數:
  • 被引用被引用:0
  • 點閱點閱:332
  • 評分評分:
  • 下載下載:12
  • 收藏至我的研究室書目清單書目收藏:0
浮動式閘極快閃記憶體由於許多問題(如耦合效應及SILC所引起的漏電)而無法滿足元件微縮發展的趨勢,因此利用電荷陷阱式快閃記憶體取代浮動式閘極結構元件是未來發展的趨勢。然而傳統SONOS元件以氮化矽作為儲存層的結構,在發展到次微米以下就無法再以降低穿隧氧化層厚度來提升元件的操作效率,因此便引進了高介電材料來取代傳統ONO結構以提升元件操作效能,但此時面臨到的將是抹除速度與電荷保持力之間的trade-off問題。
本實驗將利用不同高介電係數的材料與氮化矽搭配,以堆疊的方式堆疊出電荷儲存層。研究主要是利用不同材料具有不同的特性,配合堆疊的結構,藉著電荷陷阱密度的多寡、能階大小的改變、K值影響分壓的不同、陷阱能階等種種特性,配合能帶工程堆疊出最佳特性的電荷儲存層。本論文研究的方向主要分為下列三項:
1.探討高介電材料與氮化矽的搭配三明治結構堆疊來做電荷儲存層,將其應用在電荷陷阱式快閃記憶體,討論其對元件特性研究。
2. 討論Si3N4/SiO2/ HfxAlyO結構電荷儲存層應用於電荷陷阱式快閃記憶體,對元件特性的影響。由第一項討論可發現NAN結構可有效同時改善P/E速度及電荷保持力,如何更近一步提升保持力,是本項實驗所要做的。
3. 將各種能帶工程應用於電荷儲存層的電荷陷阱式快閃記憶體元件特性的影響。本章以氮化矽與高介電的材料來堆疊出雙層結構、三明治結構以及階梯式能階結構的快閃記憶體電容元件,對其特性做一研究。
由實驗結果可發現,引進能帶工程,若是利用能隙大小的不同,堆疊出適當結構,將有助於在不犧牲抹除速度下提升電荷保持力。

1.Improvement of P/E speed for NAN structure trapping layer
higher charge tunneling efficiency
lower Ig

2.Trapped charge detrap easier for HfO2 compared with
Si3N4,but that’s a trade-off : erasing speed ? retention

3.Improvement of endurance characteristics for NAN
structure compared with single Si3N4 trapping layer
barrier oxide(Al2O3) reduces the trap generation during
cycling

4.Simultaneous improvement in P/E speed and retention for
Si3N4/Al2O3/HfO2 structure

目錄
摘要.......................................................i
致謝......................................................ii
目錄.....................................................iii
圖目錄....................................................iv
表目錄.....................................................x


第一章 序論...............................................1
1.1 前言...................................................1
1.2 快閃記憶體面臨的問題...................................2
1.3 電荷陷阱式快閃記憶體的結構及其優缺點...................2
1.4 High-K材料應用於快閃記憶體的儲存層上...................4
1.5 各章摘要...............................................6


第二章 快閃記憶體元件操作方法............................13
2.1 寫入與抹除方法........................................13
2.1.1 通道熱電子注入寫入...............................13
2.1.2 FN穿隧寫入.......................................14
2.1.3 FN穿隧抹除.......................................14
2.2 電荷保持力............................................15
2.3 耐力..................................................16
2.4 干擾..................................................17


第三章 實驗規劃與元件製程................................27
3.1 實驗規畫..............................................27
3.2 電容元件製程..........................................28
3.2.1 前段製程............................................28
3.2.2 成長穿隧氧化層......................................28
3.2.3 沉積電荷儲存層及阻擋氧化層..........................28
3.2.4 後段製程............................................29


第四章 高介電材料與氮化矽搭配三明治(NAN)結構之電荷儲存層對電荷陷阱式快閃記憶體元件特性之研究......................33
4.1 研究背景與目的.......................................33
4.2 實驗製程與規劃........................................35
4.3 實驗結果與討論........................................35
4.4 結論..................................................40


第五章 SiO2對NAN結構電荷儲存層之電荷陷阱式快閃記憶體元 件特性之影響..............................................55
5.1 研究背景與目的........................................55
5.2 實驗製程與規劃........................................56
5.3 實驗結果與討論........................................57
5.4 NAN結構與NON結構電荷儲存層元件特性之比較與分析........61
5.5 結論..................................................61


第六章 能帶工程電荷儲存層應用於電荷陷阱式快閃記憶體元件特性之研究..................................................74
6.1 研究背景與目的........................................75
6.2 實驗製程與規劃........................................76
6.3 實驗結果與討論........................................77
6.4 結論..................................................80


第七章 結論與建議......................................94
7.1 結論..................................................94
7.2 建議..................................................95


圖目錄

圖1-1浮動式閘極結構快閃記憶體示圖..........................8
圖1-2 SONOS-type快閃記憶體示意圖...........................8
圖1-3浮動式閘極結構快閃記憶體儲存能帶圖[2].................9
圖1-4 SONOS-type快閃記憶體電荷儲存時能帶圖[3]..............9
圖1-5 SONOS-type快閃記憶體寫入之能帶圖[3].................10
圖1-6 SONOS-type快閃記憶體抹除之能帶圖[3].................10
圖1-7 HfO2的XRD圖[5]......................................11
圖1-8不同Hf/Al組成比在PDA溫度為600度的XRD圖[7]............11
圖1-9 HfO2添加不同比例的Al對結晶溫度及介電常數的影響[8]...12
圖2-1通道熱電子注入示意圖.................................19
圖2-2通道熱電子注入能帶圖.................................19
圖2-3通道F-N穿隧寫入能帶圖................................20
圖2-4四種穿隧寫入示意圖[13]...............................21
圖2-5通道F-N穿隧抹除能帶圖................................22
圖2-6電子流失路徑示意圖[17] ..............................22
圖2-7源極帶對帶穿隧所產生的電子電洞流向...................23
圖2-8快閃記憶體耐力特性示意圖.............................23
圖2-9(a)源極(b)源極-閘極(c)通道抹除示意圖.................24
圖2-10陣列中的(a)汲極干擾與(b)閘極干擾示意圖..............26
圖3-1多功能真空濺鍍系統濺鍍TaN500?硐PAl-Si-Cu3000??........31
圖3-2定義電容並蝕刻後的元件結構示意圖.....................31
圖3-3實驗電容元件完成後結構示意圖.........................32
圖4-1 實驗三明治堆疊電荷儲存層結構示意圖..................43
圖4-2 (a)單層Si3N4、(b)HfO2/ Al2O3/ HfO2、(c)HfA1O / Al2O3/HfA1O、(d)Si3N4/ Al2O3/ HfO2寫入下的操作時間對平帶電壓差圖......................................................45
圖4-3不同電荷儲存層在+16V寫入時,操作時間對平帶電壓差圖...45
圖4-4不同電荷儲存層在+13V寫入時,操作時間對平帶電壓差圖...46
圖4-5不同電荷儲存層在+16V寫入時,平帶電壓差達2V所需時間圖.46
圖4-6 Si3N4/ Al2O3/ HfO2寫入時能帶示意圖..................47
圖4-7(a)單層Si3N4、(b)HfO2/ Al2O3/ HfO2、(c)HfA1O / Al2O3/HfA1O、(d)Si3N4/ Al2O3/HfO2在不同電壓抹除下的操作時間對平帶電壓差圖............................................49
圖4-8不同電荷儲存層在-16V抹除時,操作時間對平帶電壓差圖...49
圖4-9不同電荷儲存層在-16V抹除時,平帶電壓差達2V所需時間圖.50
圖4-10 Si3N4/ Al2O3/ HfO2抹除時能帶示意圖.................50
圖4-11不同電荷儲存層之電荷保持力比較圖....................51
圖4-12(a)不同電荷儲存層的平帶電壓差對操作時間圖(b)不同電荷儲存層在相同時間下達到相同VFBShift所需操作電壓圖............52
圖4-13各種條件電荷儲存層的耐力測試圖:(a) Si3N4 (b) HfO2/ Al2O3/ HfO2 (c) HfAlO/ Al2O3/ HfAlO (d)Si3N4/Al2O3/HfO2...54
圖5-1 實驗三明治堆疊電荷儲存層結構示意圖..................64
圖5-2為不同電荷儲存層結構分別在+13V、+15V、+16V寫入時,操作時間對平帶電壓差圖........................................66
圖5-3不同電荷儲存層在+16V寫入時,操作時間對平帶電壓差圖...67
圖5-4不同電荷儲存層在+16V寫入時,平帶電壓差達2V所需時間圖.67
圖5-5 Si3N4/ SiO2/ HfO2寫入時能帶示意圖...................68
圖5-6不同電荷儲存層結構分別在-13 V、-15V、-16V抹除時,操作時間對平帶電壓差圖..........................................70
圖5-7不同電荷儲存層在-16V抹除時,操作時間對平帶電壓差圖...71
圖5-8不同電荷儲存層在-16V抹除時,平帶電壓差達2V所需時間圖.71
圖5-9 Si3N4/ Al2O3/ HfO2堆疊結構抹除時能帶示意圖..........72
圖5-10不同電荷儲存層之電荷保持力比較圖....................72
圖5-11電荷保持力之能帶示意圖..............................73
圖5-12為各種條件電荷儲存層的耐力測試圖:(a) Si3N4/SiO2/Si3N4 (b) Si3N4/SiO2/ HfO2 (c) Si3N4/SiO2/HfAlO(4:1) (d) Si3N4/SiO2/HfAlO(1:1)(e) Si3N4/SiO2/HfAlO(1:4)............73
圖6-1應用能帶工程於電荷儲存層的記憶體電容結構示意圖.......86
圖6-2 (a)單層Si3N4、(b) Si3N4/ HfO2、(c) Si3N4/ Al2O3/ HfO2、(d)Si3N4/ Al2O3/ HfA1O(1:1)、(e) Si3N4/ HfA1O(2:1)/ HfO2在不同電壓寫入的時間對平帶電壓差圖....................89
圖6-3不同電荷儲存層在+16V寫入時,操作時間對平帶電壓差圖...89
圖6-4不同電荷儲存層在+16V寫入時,平帶電壓差達2V所需時間圖.90
圖6-5(a)單層Si3N4、(b) Si3N4/ HfO2、(c) Si3N4/ Al2O3/ HfO2、(d)Si3N4/ Al2O3/ HfA1O(1:1)、(e) Si3N4/ HfA1O(2:1)/ HfO2不同電壓抹除下的操作時間對平帶電壓差圖........................90
圖6-6不同電荷儲存層在-16V抹除時,操作時間對平帶電壓差圖...93
圖6-7不同電荷儲存層在-16V抹除時,平帶電壓差達2V所需時間圖.94
圖6-8不同電荷儲存層之電荷保持力比較圖.....................94
圖6-9 TANOS結構與能帶工程電荷儲存層元件之操作電壓比較(a) Si3N4/Al2O3/HfO2(b) Si3N4/HfAlO/HfO2(c) Si3N4/HfO2........95
圖6-10不同電荷儲存層在相同時間下達到相同VFBShift所需操作電壓圖........................................................96
圖6-11不同條件電荷儲存層的耐力測試圖(a)單層Si3N4、(b) Si3N4/ HfO2、(c) Si3N4/ Al2O3/ HfO2、(d)Si3N4/ Al2O3/ HfA1O(1:1)、(e) Si3N4/ HfA1O(2:1)/ HfO2........................97



表目錄


表4-1 高介電材料之k值及其他數............................42
表4-2 實驗元件製程條件...................................42
表5-1 高介電材料之k值及其他數............................63
表5-2 實驗元件製程條件...................................63
表6-1 高介電材料之k值及其他數............................85
表6-2實驗元件製程條件....................................85

參考文獻
[1] Harry Pon , et al. , “Technology Scaling Impact on NOR and NAND Flash Memories and Their Applications” , International Conference on Solid-State and Integrated Circuit Technology , Oct. 2006 , page(s):697-700
[2] Min She, “semiconductor Flash Memory Scaling” , University of California, Berkeley , Doctor of Philosophy , 2003
[3] A. Paul, Ch. Sridhar, et al, “Comprehensive Simulation of Program, Erase and
Retention in Charge Trapping Flash Memories” International Device Electron Meeting , 2006 , page(s)1-4
[4]Y. N. Tan, et al. , ” Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer” IEEE Transactions on Electron Device Device,Vol.51 , No.7, 2004, page(s): 1143- 1147
[5]J. V. Houdt, et al. , ”High-k materials for nonvolatile memory applications”, International Reliability Physics Symposium , April 17-21,2005 , page(s):234-239
[6]T. Sugizaki, M. Kobayashi, et al. , “Novel Multi-bit SONOS Type Flash Memory using a High-k Charge Trapping Layer” , VLSI Technology Symposium , 2003 , page(s):27-18
[7]Y. N. Tan, et al., “High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation” , International Electron Device Meeting , 2004 , page(s):889-892
[8]M. S. Joo, et al., ”Dependence of Chemical Composition Ratio on Electrical
Properties of HfO2 Al2O3 Gate Dielectric” , Japanese Journal of Applied Physics. , No.3A, page(s):1220-1222 , March , 2003
[9]W.J. Zhu , et al. ”Effect of Al Inclusion in HfO2 on the physical and electrical properties of the dielectrics”, IEEE Electron Devices Letters,Vol.23,NO.11, Page(s):649-651,2002
[10]G. Molas et al. , “Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications” International Electron Device Meeting , 2007 , page(s):453-456
[11]Y. N. Tan , “Hafnium Aluminum Oxide as Charge Storage and Blocking-Oxide Layers in SONOS-type Nonvolatile Memory for High-Speed Operation” , IEEE Transactions on Electron Devices , April 2006 , Page(s):654-662
[12] Z. L. Huo et al. , “Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory” , VLSI Technology Symposium , 2007 , page(s):138-139
[13]J. Bu, et al., “Retention reliability enhanced SONOS NVSM with scaled programming voltage” , IEEE Aerospace Conference paper , P5-2383 5-2390, 2002
[14]M. H. White, et al. , “A low voltage SONOS nonvolatile semiconductor memory technology” , IEEE transactions on Components, Packaging, and Manufacturing Technology , June 1997 , page(s):190-195,
[15]W.J. Tsai, et al., “Data retention behavior of a SONOS type two-bit storage flash memory cell” , International Electron Device Meeting , 2001 , Page(s):32.6.1-32.6.4
[16]K. T. San , et al. , “Effects of erase source bias on Flash EPROM device reliability” , IEEE Transactions on Electron Devices, V January 1995 , page(s):150-159
[17]M. Chang et al. , “Charge loss behavior of a metal alumina nitride oxide silicon type flash memory cell with different levels of charge injection” , Applied Physics Letters , 2008 , page(s):232105-232105-3
[18]G. Verma, et al. , “Reliability Performance of ETOX Based Flash Memory” , International Reliability Physics Symposium , 1998 , page(s):158-166
[19]S. Haddad, et al. , “Degradation Due to Hole Trapping in Flash memory cells” , IEEE Electron Dev. Letters , 1989 , page(s):117-119
[20]Y. Shin et al, ”A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs” , International Electron Device Meeting , 2005 , page(s):327-330
[21] K.T. Park, et al , “A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond” , VLSI Technology Symposium , 2006, page(s):19-20
[22] Sandhya C. et al, “Nitride Engineering and the effect of interfaces on charge trap flash performance and reliability” , International Reliability Physics Symposium ,2008 , page(s):406-411
[23] Z. Huo et al., “Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory”, VLSI Technology Symposium , 2007, page(s):138-139.
[24]N. Umezawa , et al , “The role of nitrogen incorporation in Hf-based High-k dielectrics : reduction in electron charge traps” , Solid-State Device Research Conference , 2005 , page(s):201-204
[25]Y.Q. Wang , et al., “Fast erasing and highly reliable MONOS type memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack” , International Electron Device Meeting , 2006 , page(s):1-4
[26]T.S. Chen , et al., “Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer” Electron Device Letters , 2004 , page(s):205-207
[27]Gabriel Molas , ”Investigation of Hafnium-aluminum alloys in views of integration an interpoly dielectrics of future Flash memories” , Solid-State Electronics , 2007
[28] G.Zhang et al. , “Potential Well Engineering by Partial Oxidation of TiN for High-Speed and Low-Voltage Flash Memory with Good 125oC Data Retention and Excellent Endurance” , International Electron Device Meeting , 2009 , page(s):1-4
[29] P.H. Tsai, Kuei-Shu Chang-Liao et al. , “Charge-Trapping-Type Flash Memory Device With Stacked High-k Charge-Trapping Layer” , Electron Device Letters , July 2009 , page(s):775-777
[30]ITRS , Process Integration Devices and the structures , 2007 , pp. 35-37
[31] K. Kim , “Technology for sub-50nm DRAM and NAND Flash manufacturing” , International Electron Device Meeting , 2005 , page(s):333-336
[32] Y. Park , “Highly Manufacturalbe 32Gb Multi-Level NAND Flash memory with 0.0098um2 cell size using TANOS(Si-Oxide-Al2O3-TAN) Cell Technology” , International Electron Device Meeting , 2006 , page(s):54-55
[33] S. Y. Wang et al, “Reliability And Processing Effects Of Band-gap Engineered SONOS (BE-SONOS) Flash Memory”, International Reliability Physics Symposium , 2007, page(s):171-176.
[34] K. H. Wu et al, “SONOS Device With Tapered Band-gap Nitride Layer”, Electron Device Letters 2005, page(s):987-992.
[35] H.C. Chien et al., “Two-bit SONOS type Flash using a band engineering in the nitride layer”, Microelectronics. Eng., 2005, pp. 256
[36] G. Zhang, “Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-k Trapping Layer”, IEEE Tran. on Electron Device Letters, 2007, page(s):3317-3324
[37] P.H. Tsai, Kuei-Shu Chang-Liao, et al. , “Novel SONOS-Type Nonvolatile Memory Device with Suitable Band Offset in HfAlO Charge-Trapping Layer” , VLSI Technology Symposium , 2007 , page(s): 1 - 2
[38] S. Jeon et al. , “High Work-function metal gate and High-k dielectrics for Charge Trap Flash memory device applications” , Solid-State Device Research Conference , December 2005 , page(s):325-328
[39] S. Jeon et al., “Impact of metal work function on memory properties of Charge-Trap-Flash devices using Fowler–Nordheim P/E Mode” , Electron Device Letters , June 2006 , page(s):486-488
[40] Antonio Arreghini , et al., “Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells” , IEEE Transactions on Electron Devices , May 2008 , page(s):1211-1219
[41] N. Goel , et al. , “Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer” , Electron Device Letters , March 2009 , page(s):216-218
[42] S. Y. Wang et al, “Reliability and Processing Effects Of Bandgap Engineered SONOS (BE-SONOS) Flash Memory”, International Reliability Physics Symposium, 2007, page(s):171-176
[43] G.D. Wilk, et al. , “High-K gate dielectrics: Current status and material properties considerations” , Journal of Applied Physic , 2001, page(s): 5243-5275
[44] K. S. Kim , et al., “Charge Trapping Characteristics of HfO2 Layers for Tunnel-barrier-engineered Nonvolatile Memory Applications” , Journal of the Korean Physical Society , September 2009, page(s):962-965
[45] R. Singh *, Allen R. Hefner , “Reliability of SiC MOS devices” , Solid-State Electronics , 2004 ,page(s):1717–1720
[46] G. Zhang et al. , “Hot-Electron Capture for CHEI Programming in SONOS-Type Flash Memory Using High-k Trapping Layer” , Transactions on Electron Devices , 2008 , page(s): 1502-1510
[47] G. Zhang et al. , “Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-k Trapping Layer” , Transactions on Electron Devices , 2007, page(s): 3317 - 3324

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top