臺灣博碩士論文加值系統

Abstract

Flash memory is import and has been popularly used in our daily life. Two type of flash memory devices are proposed to circumvent the scaling down limitation of the conventional planar technology and to improve the operation performance. One is based on the used of stack tunnel dielectric and the other on the used of vertical double-gate structure.
In this study, we design two groups of tunnel dielectric for flash memory devices. The first group is to used a single Si3N4 or Si3N4/SiO¬2 stack tunnel dielectric, followed by rapid-thermal-annealing (RTA); the second group is to used a single HfOxNy or HfOxNy/SiO2 stack tunnel dielectric, followed by post-deposition annealing (PDA). It is experimentally observed that flash memory devices with a stack tunnel dielectric have better operation performance than those with a single layer. In the first sample group, devices with a stack tunnel dielectric composed of a thick Si3N4 layer and a thin SiO2 layer exhibits better operating performance. For the RTA samples, flash memory devices subjected at 800oC temperature of their tunnel dielectrics exhibit better performance. In the second sample group, those with a stack tunnel dielectric composed of a thick HfOxNy layer and a thin SiO2 layer exhibits the best operation performance. For the PDA samples, the flash memory devices with an HfOxNy/SiO2 stack tunnel dielectric subjected to a PDA temperature at 850oC exhibit the best operation performance.
Various structures and operation characterization of the vertical double gate flash memory devices are studied by the device simulator MEDICI, to circumvent the scaling down limitation of the conventional planar technology. Novel vertical double gate flash memory devices with SiGe/Si heterojunction by band-gap engineering exhibits better operation performance. The Ge content in the SiGe junction of vertical double gate flash memory devices with SiGe/Si heterojunction improves operation performances.

摘要

　　快閃記憶體已愈來愈重要並廣泛地應用於日常生活中。為改善快閃記憶體之操作特性，及解決元件微縮過程中所面臨之問題，本文提出利用堆疊結構穿隧介電層之快閃記憶體，並另設計新型垂直結構搭配矽化鍺材料之快閃記憶體。
本文設計兩類之快閃記憶體穿隧介電層: 第一類為利用單層Si3N4或不同組成比之Si3N4/ SiO2堆疊結構，再配合不同溫度之快速熱處理；第二類為利用單層HfOXNY或不同組成比之 HfOXNY/ SiO2堆疊結構，再配合不同溫度之快速熱處理。 由實驗知，堆疊結構較單層穿隧介電層之操作特性佳。於第一類元件：堆疊結構之穿隧介電層中，厚的Si3N4搭配薄的SiO2堆疊結構之穿隧介電層，擁有較佳之元件操作特性；不同溫度之快速熱處理中，800 oC快速熱處理之穿隧介電層，擁有較佳之元件操作特性。於第二類元件：堆疊結構之穿隧介電層中，厚的HfOXNY搭配薄的SiO2堆疊結構之穿隧介電層，擁有最佳之元件操作特性；不同溫度之快速熱處理中，850 oC快速熱處理之穿隧介電層，擁有最佳之元件操作特性。
避免元件微縮過程中所面臨之問題，本文應用元件模擬軟體MEDICI 設計不同垂直結構並配合不同操作條件之快閃記憶體。搭配矽/矽化鍺異質接於面垂直結構雙閘極快閃記憶體，擁有較佳之元件操作特性。隨著增加矽化鍺之鍺含量於搭配矽/矽化鍺異質接面之垂直結構雙閘極快閃記憶體，快閃記憶體之操作特性跟著改善。

Contents
Abstract (in English) i
Abstract (in Chinese) iii
Acknowledgment iv
Contents v
List of Tables ix
List of Figures x
Chapter 1
Introduction 1
1.1 General Background 1
1.1.1 Flash memory classification 1
1.1.2 Tunnel dielectric limitation of flash memory device 3
1.1.3 High K material 3
1.1.4 High k dielectrics of flash memory devices 4
1.1.5 Different structures of Flash memory and MOSFET 5
1.1.5.1 SiGe MOSFET 5
1.1.5.2 Flash memory with SiGe 5
1.1.5.3 Double gate nonvolatile memory 6
1.1.5.4 Three-dimensional flash memory 6
1.2 Objective and Scope 7

Chapter 2
Experiments and Simulations 16
2.1 Process flow of flash memory 16
2.2 Operated principle of flash memory 17
2.2.1 The Lucky-Electron model of Channel-Hot-Electron- Injection 17
2.2.2 Band-to-Band Tunneling induced Hot Electron injection model 21
2.2.3 Fowler-Nordheim (FN) Tunneling 22
2.3 The MEDIC device simulator 23
Chapter 3
Flash memories with silicon nitride/silicon dioxide stack tunnel dielectric 33
3.1 Introduction 33
3.2 Experiment 34
3.3 Results and discussion 36
3.4 Conclusion 37
Chapter 4
Flash memories with HfOxNy/SiO2 stack tunnel dielectric 46
4.1 Introduction 46
4.2 Experiment 47
4.2.1 The fabrication of flash memory devices 47
4.4.2 Electrical measurements and materials analysis 49
4.3 Results and discussion 50
4.3.1 The physical characteristics of HfOxNy annealed at various temperatures 50
4.3.2 Effects of various HfOxNy/SiO2 stacks as tunnel dielectrics on the Electrical and reliability characteristics of flash devices 51
4.3.3 Effects of HfOxNy/SiO2 stack tunnel dielectrics treated by various PDA temperatures on the electrical and reliability characteristics of flash devices 53
4.4 Conclusion 55
Chapter 5
Flash memories with vertical double gate and SiGe/Si heterojunction 70
5.1 Introduction 70
5.2 Structure of vertical double gate flash memory devices 72
5.3 Simulation of vertical double gate flash memory devices 74
5.4 Results and discussion 75
5.4.1 Vertical double gate p-channel flash memory 75
5.4.2 Vertical double gate n-channel flash memory 78
5.4.3 Various Ge contents in strained Si1-xGex for vertical double flash memory device with drain side SiGe/Si heterojunction 80
5.5 Conclusion 82
Chapter 6
Conclusion and future work 102
6.1 Conclusion 102
6.2 Suggestions on Future Work 103
Reference 104
Vita 117

Reference
[1] D. L. Kencke, X. Wang, Q. Ouyang, S. Mudanai, A. Tasch, Jr., and S. K. Banerjee, “Enhanced secondary electron injection in novel SiGe flash memory devices”, IEEE International Electron Device Meeting, pp.105–108, San Francisco, CA, USA, December, 2000
[2] C. C. Wang, K. S. Chang-Liao, C. Y. Lu, and T. K. Wang, “Enhanced Band-to-Band-Tunneling-Induced Hot-Electron Injection in p-Channel Flash by Band-gap Offset Modification”, IEEE Electron Device Letter, vol. 27, no. 9, pp. 749-751, September, 2006.
[3] K. H. Yuen, T. Y. Man, A. C. K. Chan, and M. Chan, “A 2-Bit MONOS Nonvolatile Memory Cell Based on Asymmetric Double Gate MOSFET Structure”, IEEE Electron Device Letters, vol. 24, no. 8, pp. 518-520, August, 2003.
[4] Y. Fukuzumi, R. Katsumata, M. Kito, M. Kido, M. Sato, H. Tanaka, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory”, IEEE International Electron Device Meeting, pp. 449-452, Washington, DC, USA, December, 2007.
[5] M. K. Jeong, H. I. Kwon, J. H. Lee, “3-D Stacked NAND Flash String with Tube Channel Structure Using Si and SiGe Selective Etch Process”, IEEE International Memory Workshop, pp.49-50, Monterey, CA, USA, May , 2009 .
[6] H. Aochi, “BiCS Flash as a Future 3D Non-volatile Memory Technology for Ultra High Density Storage Devices”, IEEE International Memory Workshop, pp.1-2, Monterey, CA, USA, May, 2009 .
[7] P. H. Tsai, K. S. Chang-Liao, C. Y. Liu, T. K. Wang, P. J. Tzeng, C. H. Lin, L. S. Lee, and M. J. Tsai, “Novel SONOS-Type Nonvolatile Memory Device With Optimal AL Doping in HfAlO Charge-Trapping Layer”, IEEE Electron Device Letter, vol. 29, no. 3, pp. 265-268, March, 2008.
[8] H. Y. Lai, K. S, Chang-Liao, T. K. Wang, P. K. Wang, C. L. Cheng, “Performance improvement of flash memories with HfOxNy/SiO2 stack tunnel dielectrics”, Journal of Vacuum Science and Technology B, vol. 24, pp. 1683-1688, Jul/Aug, 2006.
[9] H. Y. Lai, K. S. Chang-Liao, T. K. Wang, and Z. F. Song, “Improved Performance of Flash Memory by Silicon Nitride/Silicon Dioxide Stack Tunnel Dielectric”, IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 243~246, Hinshcu, Taiwan, July, 2004.
[10] C. H. Ho, K. S. Chang-Liao, C. Y. Lu, C. C. Lu, T. K. Wang, “Employing vertical dielectric layers to improve the operation performance of flash memory devices”, Microelectronics Reliability, vol. 49, pp. 371–376, 2009.
[11] C. H. Ho, K. S. Chang-Liao, Y. N. Huang, T. K. Wang, T. C. Lu, “Performance and reliability improvement of flash device by a novel programming method”, Microelectronics Reliability, vol. 47, pp. 967–971, 2007.
[12] J. Sarkar, S. Dey, D. Shahrjerdi, and S. K. Banerjee, “Vertical Flash Memory Cell With Nanocrystal Floating Gate for Ultradense Integration and Good Retention”, IEEE Electron Device Letters, vol. 28, no.5, pp. 449-451, May, 2007.
[13] L. M. Weltzer and S. K. Banerjee , “Enhanced CHISEL programming in flash memory devices with SiGe buried layer”, IEEE Non-Volatile Memory Technology Symposium, pp. 31–33, Orlando, FL, USA, November, 2004.
[14] S. H. Lee, M. Park, B. Y. Choi, S. K. Sung, T. H. Kim, B. Ju, D. C. Kim, C. H. Lee, K. Kim, J. Choi, and K. Kim, “Investigation on the Retention Reliability of Scaled SiO2/AlxOy/SiO2 Inter-PolyDielectrics for NAND Flash Cell Arrays”, IEEE Electron Device Letters, vol. 31, no. 4, pp. 266-268, April, 2010.
[15] M. Y. Wua, S. H. Daia, K. H. Leea, S. F. Hub, and Y. C. Kinga, “Band-to-band tunneling induced substrate hot electron injection (BBISHE) to perform programming for NOR flash memory”, Solid State Electronics, vol. 50, pp. 309–315, 2006.
[16] Y .Wang, Y. Zhao, B. M. Khan, C. L. Doherty, J. D. Krayer, M. H. White, “A novel SONOS nonvolatile flash memory device using substrate hot-hole injection for write and gate tunneling for erase”, Solid State Electronics, vol. 48, pp.2031–2034, 2004.
[17] X. Lin, and M. Chan, “A Highly Scalable Opposite Side Floating-Gate Flash Memory Cell”, IEEE Transactions on Electron Devices, vol. 52, no. 9, September, 2005.
[18] F. Zhou, Y. Cai, R. Huang , Y. Li, X. Shan, J. Liu, A. Guo, X. Zhang, and Y. Wang,
“VDNROM: A Novel Four-Bits-Per-Cell Vertical Channel Dual-Nitride-Trapping-Layer ROM for High Density Flash Memory Applications”, Proceeding of the European Solid State Device Research conference, pp. 226-229, Montreux, Switzerland, September 2006.
[19] C. Shen, J. Pu, M. F. Li, and B. J. Cho, “P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices”, IEEE Transactions on Electron Devices, vol. 54, no. 8, August, 2007.
[20] X. B. Lu, P. F. Lee, and J. Y. Dai, “Effects of forming gas annealing on the memory characteristics of Ge nanocrystals embedded in LaAlO3 high-kdielectrics for flash memory device application”, Thin Solid Films, vol.513, pp. 182~186, 2006.
[21] J. J. Lee, X. Wang, W. Bai, N. Lu, and D. L. Kwong, “Theoretical and Experimental Investigation of Si Nanocrystal Memory Device With HfO2 High-k Tunneling Dielectric” , IEEE Transactions on Electron Devices, vol. 50, no. 10, pp. 2067~2072, October, 2003.
[22] S. Lai, “Tunnel Oxide and ETOX Flash Scaling Limitation”, International NonVolatile Memory Technology conference, pp. 6-7, Albuquerque, NM, USA, June 1998.
[23] H. Y. Lai, K. S. Chang-Liao, T. K. Wang, and C. F. Sung, “Operation Characterization of Flash Memory with Silicon Nitride/Silicon Dioxide Stack Tunnel Dielectric”, Japanese Journal of Applied Physics, vol. 44, no. 14, pp.435–438, 2005.
[24] P. Blomme, J. V. Houdt, and K. D. Meyer, “Write/Erase Cycling Endurance of Memory Cells With SiO2/HfO2 Tunnel Dielectric”, IEEE Transactions on Device and Materials Reliability, vol.4, no.3, September, pp. 345~352, 2004.
[25] D. W. Kim, T. Kim, and S. K. Banerjee, “Memory Characterization of SiGe Quantum Dot Flash Memories With HfO2 and SiO2 Tunneling Dielectrics”, IEEE Transactions on Electron Devices, vol.50, no.9, September, pp. 1823~1829, 2003.
[26] B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. De Meyer, “VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices”, IEEE Electron Device Letters, vol. 24, n0.2, February, pp. 99~101, 2003.
[27] T. P. Lee, C. Jang, B. A. Haselden, M. Dong, S. Park, L. Bartholomew, H. Chatham, and Y. Senzakib, “Equivalent oxide thickness reduction of interpoly dielectric using ALD-Al2O3 for flash device application”, Journal of Vacuum Science and Technology B, vol. 22, pp. 2295~2298, Sep/Oct , 2004.
[28] W. H. Lee, J. T. Clemens, R. C. Keller, and L. Manchanda, “A Novel High K Inter-Poly Dielectric (IPD), Al2O3 for Low Voltage/High Speed Flash Memories: Erasing in msecs at 3.3V”, Symposium on VLSI Technology Digest of Technical Papers, pp. 117~118, 1997.
[29] R. Oez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash Memory “, invited paper, proceedings of the IEEE, vol. 91, no. 4, April, 2003.
[30] Y. Itoh, M. Momodomi, R. Shirota, Y. lwata, R. Nakayama, R. Kirisawa, T. Tanaka, K. Toita, S. Inoue, and F. Masuoka, “An Experimental 4Mb CMOS EEPROM with a NAND Structured Cell”, 1989 IEEE International Solid State Circuits Conference, pp134-135, 1989.
[31] T. Tanaka, Y. Tanaka, H. Nakamura, K. Sakui, H. Oodaira, R. Shirota, K. Ohuchi, F. Masuoka, H. Hara “A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory”, IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp.1366-1373, November 1994.
[32] International Technology Roadmap for Semiconductors, 2009.
[33] Wilk, G. D. Wallace, R. M. Anthony, J. M, “High-κ gate dielectrics: Current status and materials properties considerations”, Journal of Applied Physics, vol. 89, no.10, pp. 5243 – 5275, May, 2010.
[34] C. L. Cheng, C. Y. Lu, K. S. Chang-Liao, C. H. Huang, S. H. Wang, and T. K. Wang, “Effects of Interstitial Oxygen Defects at HfOxNy/Si Interface on Electrical Characteristics of MOS Devices”, IEEE Transactions on Electron Devices, vol. 53, no.1, pp. 63-70, 2006.
[35] M. Liu, Q. Fang, G. He, L. Q. Zhu, L. D. Zhang, “Characterization of HfOxNy gate dielectrics using a hafnium oxide as target”, Applied Surface Science, vol. 252, pp. 8673-8676, 2006.
[36] C. S. Kang, H. J. Cho, R. Choi, Y. H .Kim, C. Y. Kang, S. J. Rhee, C. Choi, M. S. Akbar, and J. C. Lee, “The Electrical and Material Characterization of Hafnium Oxynitride Gate Dielectrics With TaN-Gate Electrode”, IEEE Transactions on Electron Devices vol. 51, no. 2, February, pp.220~227, 2004.
[37] C. T. Yang, K. S C-Liao, H. C. Chang, B. S. Sahu, T. C. Wanga, T. K. Wanga, W. F. Wu, “Integration of HfxTay Nmetal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications”, Microelectronic Engineering, vol. 84, no.12, pp. 2916–2920, 2007.
[38] C. H. Choi, T. S. Jeon, R. Clark, and D. L. Kwong, “Electrical Properties and Thermal Stability of CVD HfOxNy Gate Dielectric With Poly-Si Gate Electrode”, IEEE Electron Device Letters, vol.24, pp.215~217, April, 2003.
[39] C. W. Liu, S. Maikap, and C. Y. Yu, “Mobility-enhancement technologies”, IEEE Circuits & Devices Magazine, vol. 21, no. 3, pp. 21–36, May/Jun. 2005.
[40] S. V. Vandebroek, E. F. CrabbC, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork, J. B. Johnson, “SiGe-Channel Heterojunction p-MOSFET’s”, IEEE Transaction on Electron Devices, vol. 41, no. 1, pp. 90–101, Jan. 1994.
[41] S. V. Vandebroek, Member, F. Crabbk, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork, A. C. Megdanis, C. L. Stanis, A. A. Bright, G. M. W. Kroesen, and A. C. Warren, “High-Mobility Modulation-Doped Graded SiGe-Channel p-MOSFET ’ s”, IEEE Electron Device Letters, vol. 12, no. 8, August, pp. 447-449, 1991.
[42] T. Mizuno, N. Sugiyama, T. Tezuka, and S. I. Takagi, “Novel SOI p-Channel MOSFETs With Higher Strain in Si Channel Using Double SiGe Heterostructures”, IEEE Transactions on Electron Devices, vol. 49, no. 1, January, pp. 7-14, 2002.
[43] Q. Ouyang, X. D. Chen, S. Mudanai, D. L. Kencke, X. Wang, A. F. Tasch, L. F. Register, and S. K. Banerjee, “Two-Dimensional Bandgap Engineering in a Novel Si/SiGe pMOSFET with Enhanced Device Performance and Scalability”, IEEE International conference on simulation of semiconductor process and devices, pp. 151-154, Seattle, WA , USA , September 2000.
[44] Q. Ouyang, X. Chen, S. P. Mudanai, X. Wang, D. L. Kencke, A. Tasch, L. F. Register, and S. K. Banerjee, “A Novel Si/SiGe Heterojunction pMOSFET with Reduced Short-Channel Effects and Enhanced Drive Current”, IEEE Transactions on Electron Devices, vol. 47, no. 10, pp. 1943-1949, October, 2000.
[45] S. Tam, P. Ko, and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFETs”, IEEE Transactions on Electron Devices, vol. 31, no. 9, pp. 1116–1125, September, 1984.
[46] Medici User’s Manual, 2006.
[47] K. Hasnat, C. F. Yeap, S. Jallepalli, W. K. Shih, S. A. Hareland, V. M. Agostinelli, A. F. Tasch, and C. M. Maziar, “A Pseudo-Lucky Electron Model for Simulation of Electron Gate Current in Submicron NMOSFET’S”, IEEE Transactions on Electron Devices, vol. 43, no. 8, pp.1264-1273, August, 1996.
[48] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka, and H. Miyoshi, “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cell”, IEEE International Electron Device Meeting, pp.279–282, Washington, DC, USA, December 1995.
[49] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika, and S. Satoh, “Device Characteristics of 0.35 m P-Channel DINOR Flash Memory Using Band-to-Band Tunneling-Induced Hot Electron (BBHE) Programming”, IEEE Transactions on Electron Devices, vol. 46, no.9, pp. 1866-1871, 1999.
[50] D. W. Kim, T. Kim, and S. K. Banerjee, “Memory Characterization of SiGe Quantum Dot Flash Memories with HfO2 and SiO2 Tunneling Dielectrics”, IEEE Transaction on Electron Devices, vol. 50, pp. 1823-1829, 2003.
[51] M. Lenzlinger, and E. H. Show, “Fowler-Nordheim Tunneling into Thermally Grown SiO2”, Journal of Applied Physics, vol. 40, pp. 278-283, 1969.
[52] M. She, T. JaeKing, C. Hu, W. Zhu, Z. Luo, J. P. Han, and T. P. Ma, “JVD Silicon Nitride as Tunnel Dielectric in p-Channel Flash Memory”, IEEE Electron Device Letters, vol. 23, no. 2, pp. 91-93, February, 2002.
[53] Y. Wu, Y. M. Lee and G. Lucovsky, “1.6nm Oxide Equivalent Gate Dielectrics Using Nitride/Oxide (N/O) Composites Prepared by RPECVD/Oxidation Process”, IEEE Electron Device Letters, vol. 21, no. 3, pp.116-118, 2000.
[54] Y. Shi, X. Wang, T. P. Ma, “Electrical Properties of High-Quality Ultrathin Nitride/Oxide Stack Dielectrics”, IEEE Transactions on Electron Devices, vol. 46, no.2, pp-362-368, 1999.
[55] G. Q. Lo, S. Ito, D. L. Kwong, V. K. Mathews and P. C. Fazan, “High Reliable SiO2/Si3N4 Stacked Dielectric on Rapid-Thermal-Nitrided Rugged Polysilicon for High-Density DRAM’s”, IEEE Electron Device Letter, vol.13, no.7, pp.372-374, 1992.
[56] A. B. Joshi, R. A. Mann, L. Chung, T. H. Cho, B. W. Min and D. L. Kwong, “Reduction of RIE-Damage by N2O-Anneal of Thermal Gate Oxide”, IEEE Transaction on Semiconductor Manufacturing, vol.11, no.3, pp-495-500, 1998.
[57] K. S. C-Liao and P. J. Tzeng, “Boron penetration reduction and FN stress hardness improvement in MOS capacitors by gate oxides rapid-thermal-annealed in N2O”, Solid-State Electronics, vol. 42, pp. 425-427, 1998.
[58] R. P. Vasquez and A. Madhukar, “ Strain-dependent defect formation kinetics and a correlation betwen flatband voltage and nitrogen distribution in thermally nitrided SiOXNY/Si structuree”, Applied Physics Letter, vol.47, pp.988-1000, 1985.
[59] Q D. M. Khosru, A. Nakajima, T. Yoshimoto and S. Yokoyama, ” High-quality NH3-annealed atomic layer deposited Si-nitride/SiO2 stack gate dielectrics for sub-100nm technology generations”, Solid-State Electronics, vol.46, pp.1659-1664, 2002.
[60] C. L. Cheng, K. S. Chang-Liao, C. H. Huang, and T. K. Wang, “Effects of denuded zone of Si(111) surface on current conduction and charge trapping of HfOxNy gate dielectric in metal-oxide-semiconductor devices”, Applied Physics Letters vol. 85, no. 20, pp. 4723~4725, 2004.
[61] C. T. Yang, K. S. C. Liao, H. C. Chang, C. H. Fu, T. K. Wang, W. F. Tsai, C. F. Ai, and W. F. Wu, “Electrical Characteristics and Thermal Stability of HfxTaySizN Metal Gate Electrode for Advanced MOS Devices”, IEEE Transactions on Electron Devices vol. 55, no. 11, November, pp.3259~3266, 2008.
[62] J. R. Hauser and K. Ahmed, “Characterization of ultrathin oxides using electrical C-V and I-V measurement”, Char. Metrol. ULSI Technology, pp. 235-230, 1998.
[63] H. Fujioka, S. Kamohara, Y. C. King, and K. Yang, “QMCV simulator”, online available http://www-device.eecs.berkeley.edu/qmcv/index.shtml
[64] H. Y. Guo and Z. G. Ye, “Electric characterization of HfO2 thin films prepared by chemical solution deposition”, Materials Science and Engineering B, vol.120, pp. 68-71, 2005.
[65]N. Terasawa, K. Akimoto, Y. Mizuno, A. Ichimiya, K. Sumitani, T. Takahashi, X.W. Zhang, H. Sugiyama, H. Kawata, T. Nabatame, and A. Toriumi, “Crystallization process of high-k gate dielectrics studied by surface X-ray diffraction”, Applied Surface Science, vol. 244, pp. 16-20, 2005.
[66] K. J. Choi, J. H. Kim, S. G. Yoon, and W. C. Shin, “Structural and electrical properties of HfOxNy and HfO2 gate dielectrics in TaN gated nMOS CAP and nMOSFET devices”, Journal of Vacuum Science and Technology B, vol. 22, no. 4, pp. 1755-1758, 2004.
[67] C. S. Kuo, J. F. Hsu, S. W. Huang, L. S. Lee, M. J. Tsai, and J. G. Hwu, “High-k Al2O3 Gate Dielectrics Prepared Oxidation of Aluminum Film in Nitric Acid Followed by High-Temperature Annealing”, IEEE Transactions on Electron Devices, vol. 51, no. 6, June, pp. 854-858, 2004.
[68] C. D. Young, G. Bersuker, G. A. Brown, C. Lim, P. Lysaght, P. Zeitzoff, R. W. Murto, and H. R. Huff, “Charge Trapping in MOCVD Hafnium-Based Gate Dielectric Stack Stuctures and Its Impact on Device Performance”, Integrated Reliability Workshop Final Report, IEEE, pp. 28-35, South Lake Tahoe, CA, USA, October 2003.
[69]N. Bhat, P. P. Apte, and K. C. Saraswat, “Charge Trap Generation in LPCVD Oxides Under High Field Stressing”, IEEE Transactions on Electron Devices, vol. 43, no. 4, April, pp. 554-560, 1996.
[70] C. L. Cheng, K. S. Chang-Liao, T. C. Wang, T. K. Wang, and H. C. H. Wang, “Thermal Stability of HfxTayN Metal Gate Electrodes for Advanced MOS Devices”, IEEE Electron Device Letters, vol. 27, no. 3, pp. 148-150, 2006.
[71] D.J. Paul,“Si/SiGe heterostructures: From material and physics to devices and circuits”, Semiconductor Science and Technology, vol. 19, no. 10, pp.75–108, October, 2004.
[72]R. Peopleand J.C. Bean, “Band alignments of coherently strained-GexSi1−x/Si heterostructures on <001> GeySi1−ysubstrates”,Applied Physics Letters, vol. 48, no. 8, pp. 538–540, February. 24, 1986.
[73] C. H. Jang, M. R. Sardela Jr., S. H. Kim, Y. J. Song, and N. E. Leea, “Strain relaxation of epitaxial SiGe layer and Ge diffusion during Ni silicidation on cap-Si/SiGe/Si(001)”, Applied Surface Science, vol. 252, issue 15, pp.5326–5330,May, 2006. in Proc. IEEE SISPAD, 2000, pp. 151-154.
[74] S. A. Parke, J .E.Moon, H. C. Wann, P. K. Ko, and C. Hu, “Design for Suppression of Gate-Induced Drain Leakage in LDD MOSFETs Using a Quasi-Two-Dimensional Analytical Model”, IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 1694–1703 , July, 1992.
[75] C. H. Lin, B. C. Hsu, M. H. Lee, and C. W. Liu ,“A Comprehensive Study of Inversion Current in MOS Tunneling Diodes”, IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2125–2130, September, 2001.
[76] S. S. Iyer, G. L. Patton, J. M. C. Stork, B. S. Meyerson, and D. L. Harame, “Heterojuction Bipolar Transistors Using Si-Ge Alloys”, IEEE Transaction Electron Devices, vol. 36, no. 10, pp. 2043-2064, Oct, 1989.
[77] E. O. Kane, “Zener Tunneling in Semiconductors”, Journal of Physical and Chemical of Solids, vol. 12, pp. 181-188, 1959.