臺灣博碩士論文加值系統

快閃式類比數位轉換器具有先天上的優勢能夠去達到高速的取樣速率。儘管快閃式類比數位轉換器有優越的取樣速率，但本身較大的功耗也成為它在許多應用上的瓶頸。在高速互補式金氧半導體類比數位轉換器的設計中，速度、功耗、精準性都是需要相互取捨考量的重要因素。隨著製程技術朝著更小的電晶體尺寸及較低的工作電壓之趨勢，快閃式類比數位轉換器也因此可以大幅降低其功耗。當互補式金氧半導體技術無止盡地趨向更小的電晶體尺寸發展時，也導致現今的深次微米電晶體必須伴隨著更低的工作電壓。然而當電晶體尺寸和工作電壓越來越縮減，卻使得快閃式類比數位轉換器產生顯著的電壓偏移，也讓它在較高的精準度設計上更加困難。目前有許多電路技術被使用來改善上述所遭遇的設計問題，像是電阻網路平均校正技術和數位校正技術，而其中的數位校正技術更是現今最主要的解決方案。在本篇論文中將提出一種新穎的數位校正技術去實現高速的類比數位轉換器。
本論文提出一個每秒轉換20億次，具有6位元解析度的快閃式類比數位轉換器，其採用樹狀佈局及數位校正技術且不具備取樣保持電路。由於在高速類比數位轉換器的前端電路設計通常會使用較小的元件尺寸，這也使得電壓偏移量增大，進而導致非線性的輸出電壓。因此一種數位校正方法將被應用去提升所提出的類比數位轉換器之效能。此外，我們藉由樹狀佈局來避免不使用取樣保持電路時可能產生的動態錯誤。實作出之類比數位轉換器在每秒轉換20億次的速度下，對於一個低頻的輸入訊號和一個有效解析度頻寬頻率的輸入訊號，其雜訊失真比分別可達到35.6dB及32.7dB。在每秒轉換20億次的速度下且操作電壓為1.2V時，該轉換器之消耗功率為28mW，其有效面積為0.56mm×0.62mm且效能指標為每階次消耗0.54微微焦耳。
另外，在本篇論文中還提出一個使用內插式平均電壓校正技巧去提升線性度和降低功耗之6位元解析度的快閃式類比數位轉換器。此轉換器利用逐次逼近演算法和最小化殘值演算法來決定校正精準度。其製程使用90奈米互補式金氧半導體製程，在每秒轉換20億次的速度下，對於一個低頻的輸入訊號和一個Nyquis頻率的輸入訊號，其雜訊失真比分別可達到36dB及33.5dB。校正後的INL與DNL峰值分別為0.36 LSB和 0.24 LSB。在每秒轉換20億次的速度下且操作電壓為1.2V時，該轉換器之消耗功率為25mW，其有效面積為0.32mm×0.62mm且效能指標為每階次消耗0.34微微焦耳。
最後，我們將兩顆晶片的設計考量與改善之處去做比較。由於沒有取樣保持電路，所以第一顆晶片僅適用於單一類比數位轉換器系統中的應用。而第二顆晶片則可以應用在多個類比數位轉換器的系統，像是時間交錯式超高速類比數位轉換器。因為第二顆晶片有較寬的校正範圍，所以比起第一顆晶片有較小的功率消耗。憑藉著較寬的校正範圍，快閃式類比數位轉換器的比較器電晶體尺寸就可以設計得更小，也因此能得到更少的動態功耗。效能總結與比較結果表格會整理在最後。

Flash-type ADCs have the inherent advantage on high-speed sampling rates. Although the flash ADC is superiority in sampling rate but its large power consumption makes itself bottleneck in many applications. Speed, power and accuracy are tradeoff in high-speed CMOS ADC design. Process technology scaling trends toward smaller transistor dimensions and low supply voltage, and thereby it leads to greatly reduce power consumption in flash ADCs. The never-ending story of CMOS technology trending toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Transistor size scaling results in significant offset voltage and supply voltage scaling makes it more difficult in higher accuracy design. In order to improving above design issues, many techniques have been proposed, such as resistor-averaging networks and digital calibrated techniques. Especially, the digital calibrated techniques are main solutions recently. In this thesis, the new idea of digital calibrated technique is proposed to realize high-speed ADCs.
First chip, using tree-type metal layout and digital calibration, a 6-bit 2-GS/s flash ADC without track-and-hold is presented. Since large offset voltages caused by using small device sizes in front-end of high-speed ADCs usually result in nonlinearity in output, a digitally calibrated method is applied to improve the performance of the proposed ADC. In addition, no track-and-hold circuit used will cause dynamic error but tree-type metal layout will avoid it. Measurement results show the ADC achieves a SNDR of 35.6 dB for a low frequency input at 2 GS/s sampling frequency, and 32.7 dB for an ERBW input frequency. The power consumption is 28 mW at 2 GS/s from a 1.2-V supply. The core area is 0.56mm × 0.62mm and the figure of merit is 0.54pJ/conv.
Second chip, a 6-bit flash ADC using reference-voltage- interpolated calibration to improve linearity and reduce power dissipation is presented. In the ADC, the digital calibration logic employs successive approximation algorithm and minimized residue algorithm to determine precise calibration levels. Implemented by 90-nm CMOS process, the proposed ADC can achieve a signal-to-noise-and-distortion ratio of 36 dB for a low input frequency and 33.5 dB for a Nyquist-rate input frequency at 2-GS/s sampling rate. The peaks of integral and differential nonlinearities after calibration are 0.36 LSB and 0.42 LSB, respectively. The power consumption is 25 mW at 2-GS/s from a 1.2-V supply. The core area is 0.32 mm × 0.62 mm, and the figure of merit is 0.34 pJ/conversion step.
Finally, we compare the two chips design considerations and improvements. The first chip is suitable only in single ADC system application due to no track-and-hold circuit. The second chip is suitable in multi-sub ADCs system application, such as time-interleaved ultra-high speed ADCs. The second chip consumes less power comparing to the first chip due to wider calibration range. Transistor size of the comparator in flash ADC can be designed smaller due to wide calibration range, and it consumes less dynamic power. Performance summary and comparison table will be shown finally.

誌謝 i
摘要 ii
Abstract iv
Table of Contents vi
List of Tables ix
List of Figures x

Chapter 1 Introduction - 1 -
1.1. High-Speed ADC Applications and Techniques - 1 -
1.2. Organization - 3 -

Chapter 2 Flash Analog-to-Digital Converters - 4 -
2.1. Flash ADC Basic Architecture and Characteristic - 4 -
2.2. Speed-Power-Accuracy Tradeoff in High-Speed ADCs - 10 -
2.3. Flash ADC Development Technology Recent Years - 17 -
2.3.1. Part A To Part E of Flash ADC Development - 18 -
2.3.2. Part F To Part H of Flash ADC Development - 22 -
2.3.3. Part I To Part K of Flash ADC Development - 29 -
2.3.4. Part L To Part O of Flash ADC Development - 41 -

Chapter 3 Design Considerations of Calibrated Flash ADC without Track-and-Hold - 55 -
3.1. Delay of Interconnections for VLSI Circuits - 56 -
3.1.1. Interconnection RC Effect - 56 -
3.1.2. Distributed RC Line - 57 -
3.2. Background of the Flash ADC - 60 -
3.2.1. Offset Considerations - 60 -
3.2.2. Validation of Dynamic Offset Without T&H - 62 -
3.2.3. Symmetric Interconnections - 66 -
3.3. Prototype Flah ADC - 69 -
3.3.1. ADC Architecture - 69 -
3.3.2. Realization and Measurement for the ADC - 72 -
3.3.3. Summary - 76 -

Chapter 4 A Reference Voltage Interpolation Based Calibration Method for Flash ADCs - 77 -
4.1. Calibration Background - 77 -
4.1.1. Offset in Input Stage - 78 -
4.1.2. Calibration Example - 80 -
4.2. Proposed Interpolated Calibration Technique - 81 -
4.2.1. Concept of Interpolation Technique for Calibration - 82 -
4.2.2. Simplified Calibration Architecture - 85 -
4.2.3. Practical Effect of Interpolation Reference Calibration - 86 -
4.2.4. Nonidealities of Reference Interpolation - 89 -
4.3. Digital Calibration Algorithm - 89 -
4.3.1. Digital Calibration Architecture - 89 -
4.3.2. Prototyping Successive Approximation Algorithm - 94 -
4.3.3. Excepted-Value Determination to Modify SAA - 96 -
4.3.4. Input Level Shifter - 97 -
4.3.5. Minimized Residue Algorithm - 98 -
4.4. Realization and Measurement for the ADC - 100 -
4.4.1. System Realization - 100 -
4.4.2. Measurement Results - 102 -

Chapter 5 Performance Comparison - 111 -

Chapter 6 Conclusions - 116 -
6.1. Conclusions - 116 -
6.2. Future Works - 116 -

Reference - 118 -

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