臺灣博碩士論文加值系統

本論文提出新改良型多輸入互斥或閘電路，它具有低成本高效能特性。新電路係採用暨有之差動疊接電壓開關傳導閘 (Differential Cascode Voltage Switch Pass Gate, DCVSPG)架構，這種電路源自於差動疊接電壓開關 (Differential Cascode Voltage Switch, DCVS)電路與傳導閘特性相結合的技術，解決DCVSL先天具有的浮接節點問題。論文中亦分析多種多輸入互斥或閘電路架構，而新提出的電路在比較功率消耗、電路延遲、佈線面積及邏輯設計靈活性，皆優於傳統電路。而新型的四輸入互斥或閘，在TSMC 0.18µm 1.8V製程技術下，其速度可達1GHz，這比傳統DCVSPG互斥或閘架構之速度增加25%，而功率消耗則比運作在800MHz之Pseudo NMOS四輸入互斥或閘架構低2%。電路的總電晶體面積，比傳統DCVSPG架構減少47%，這也遠小於工作在150MHz 之C-CMOS 與350MHz之PTL CMOS及800MHz之Pseudo NMOS 電路架構29%至93%，是所比較的電路中面積最小的。
本論文以新型簡化重組式正規基底 (Reordered normal basis)有限場乘法器(Finite field multiplier, FFM)做為多輸入互斥或閘的測試載具。電路實現時，本論文分析四種基本重組式正規基底有限場乘法器之架構與其電路連接的關係，從中，本論文亦提出了一個簡化的全平行式重組式正規基底有限場乘法器，它可節省20%的邏輯閘。搭配本論文的四輸入互斥或閘，與傳統已知最精簡的兩輸入兩級串接之DCVSPG互斥或閘比較，其電晶體數還減少7%。在同樣在CMOS 0.18µm 1.8V製程技術，工作在1GHz時脈，本論文的改良型高效率四輸入互斥或閘，其平均功率消耗僅306 mW。

The thesis proposes a new high-performance low-cost multi-input exclusive OR gate. This new circuit adopts the known Differential Cascode Voltage Switch Pass Gate (DCVSPG) architecture which was originally modified from Differential Cascode Voltage Switch (DCVS) and combined with pass transistor gates to eliminate the floating node. In thesis, some well known multi-input XOR gates were studied and analyzed, and the results show that our new proposed XOR has lower power, shorter delay, less layout area and easier design features than the traditional one. Under a TSMC 0.18µm 1.8V process technology, our new 4-input XOR gate reaches 1GHz operational speed. When compare with the known fastest traditional DCVSPG XOR, our new circuit performs even faster than 25%. The total transistor area is reduced by 29% to 93% when compare with the traditional C-CMOS at 150MHz, PTL CMOS at 350MHz, Pseudo NMOS at 800MHz, respectively. Therefore, our new multi-input XOR is the smallest one among the traditional circuits.
For verifying the effectiveness of our new XOR, a reordered normal basis finite field multiplier (FFM) is chosen being a test vehicle. Before the circuit is implemented, four basic architectures of FFM have been surveyed. Inspired by their circuit topology, we then proposed a new compact full-parallel reordered normal basis FFM, and it reduced about 20% gate count. The new compact FFM implementation results, using TSMC 0.18µm 1.8V process technology, show that our new 4-input XOR has less 7% transistor count than the known traditional smallest two-stage 2-input DCVSPG XOR gates. The total power consumption of new FFM has only 306mW at 1GHz operational speed.

摘 要 v
Abstract vi
誌 謝 vii
目 錄 viii
表 目 錄 x
圖 目 錄 xii
第一章 緒論 1
1.1 前言與動機 1
1.2 研究方法及目的 3
1.3 論文架構組織 4
第二章 高效能多輸入互斥或閘設計 6
2.1 四輸入互斥或閘電路設計及模擬 6
2.2 C-CMOS互斥或閘電路設計 10
2.3 Pseudo-NMOS 互斥或閘電路設計 13
2.4 PTL CMOS 互斥或閘電路設計 16
2.5 DCVSPG互斥或閘電路設計 18
2.6 其它架構的互斥或閘電路設計 22
2.7 高效率DCVSPG四輸入互斥或閘設計 29
第三章 有限場特性及基本運算 42
3.1 群 (Groups)、環 (Ring)、場 (Fields) 42
3.1.1 群 (Groups) 43
3.1.2 環 (Ring) 44
3.1.3 場 (Field) 45
3.2有限場 (Galois-field or Finite Field) 47
3.3 有限場基本運算 55
3.3.1 有限場加法運算 55
3.3.2有限場乘法運算 56
第四章 有限場乘法器架構 61
4.1 標準基底 (Standard basis) 61
4.2 對偶基底 (Dual basis) 65
4.3 正規基底 (Normal basis) 66
4.4 重組式正規基底有限場乘法器定義 69
4.5 傳統重組式正規基底乘法器硬體架構 70
4.5.1 並進串出有限場乘法器 71
4.5.2 串進並出有限場乘法器 72
4.5.3 混合式有限場乘法器 73
4.5.4 全平行式有限場乘法器 74
4.6 重組式正規基底有限場乘法器設計 76
第五章 高效能重組式正規基底有限場乘法器設計與模擬比較 80
5.1 高效能全平行式正規基底有限場乘法器設計 80
5.2 以DCVSPG多輸入互斥或閘設計高效能全平行式重組式正規基底有限場乘法器 85
第六章 結論 95
參考文獻 96

[1] H. Lee, “High-speed VLSI architecture for parallel Reed-Solomon decoder,” IEEE Transactions on VLSI Systems, Vol. 11, pp. 288-294, April 2003.
[2] A.H. Namin, and H.Wu, and M. Ahmadi, “A High Speed Word Level Finite Field Multiplier Using Reordered Normal Basis,” IEEE International Symposium on Circuits and Systems, pp. 3278-3281, Jun 2008.
[3] L.Song, and K.K. Parhi, “Efficient Finite Field Serial/Parallel Multiplication,” Proceedings of International Conference on Application Specific Systems, Architectures and Processors, pp. 72-82, Aug 1996.
[4] H.Wu, and M.A. Hasan, and I.F. Blake, and S. Gao, “Finite Field Multiplier Using Redundant Representation,” IEEE Transactions on Computers, Vol. 51, pp. 1306-1316, Nov 2002.
[5] S.K. Jain, and L. Song, and K.K. Parhi, “Efficient semisystolic architectures for finite-field arithmetic”, IEEE Transactions on VLSI Systems, Vol. 6, pp. 101-113, March 1998.
[6] H.T. Kung, “Why systolic architectures?,” IEEE Computer Magazine, Vol. 15, pp. 37-46, Jan 1982.
[7] K.M. Chu, and D.L. Pulfrey, “Design procedures for differential cascode voltage switch circuits,” IEEE Journal of Solid-State Circuits, Vol. 21, pp. 1082–1087, Dec 1986.
[8] K.M. Chu, and D.I. Pulfrey, “A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic,” IEEE Journal of Solid-State Circuits, Vol. SC-22, pp. 528–532, Aug 1987.
[9] F.S. Lai, and W. Hwang, “Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems” IEEE Journal of Solid-State Circuits, Vol. 32, NO. 4, April 1997.
[10] A.H. Namin, and H. Wu, and M. Ahmadi, “High Speed Word-parallel Bit-Serial Normal Basis Finite Field Multiplier and Its FPGA Implementation,” Conference Record of the Thirty-Ninth Asilomar Conference on Signals, Systems and Computers, pp. 1338-1341, Nov 2005.
[11] A.H. Namin, and H. Wu, and M. Ahmadi, “Comb Architectures for Finite Field Multiplication in F(2m),” IEEE Transactions on Computers, Vol. 56, pp. 909-916, July 2007.
[12] L. Song, and K.K. Parhi, and I. Kuroda, and T. Nishitani, “Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs,” IEEE Transactions on VLSI Systems, Vol. 8, pp. 160-172, April 2000.
[13] C.K. Koc, and B. Sunar, “Low-Complexity bit-parallel cannonical and normal basis multipliers for a class of finite fields,” 1998 IEEE International Symposium on Information Theory, Vol. 47, NO. 03, pp 353-356, March 1998.
[14] C.H. Kim, and Y. Kim, and S.Y. Ji, and I. Park, “A New Parallel Multiplier for Type II Optimal Normal Basis,” 2006 International Conference on Computational Intelligence and Security, Vol. 2, pp. 1315-1318, Nov 2006.
[15] Y.Z. Tian, and X. Bi, and Z. Niu, “Efficient Multiplier over Finite Field Represented in Type II Optimal Normal Basis,” Sixth International Conference on Intelligent Systems Design and Applications, Vol. 1, pp. 1132-1128, Oct 2006
[16] J.L. Massey, and J.K. Omura, “Computational method and apparatus for finite field arithmetic,” U.S. Patent number 4587627, May 1986.
[17] K.J. Lin, and C.W. Wu, “A Low-Cost Realization of Multiple-Input Exclusive-OR Gates,” Proceedings of the Eighth Annual IEEE International Application Specific Integrated Circuits Conference, pp. 307-310, Sept 1995.
[18] W. Shi, and M. Cai, and T. Zhong, “A Partial Parallel folding Multiplier Design for 1024 bit Modular Multiplication,” 8th International Conference on Solid-State and Integrated Circuit Technolog, pp. 2058-2060, Oct 2006.
[19] S. Veeramachaneni, and M.K. Krishna, and L. Avinash, and S.R. Puppala, and M.B.Srinivas, “Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors,” 20th International Conference on VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems, pp. 324-329, Jan 2007.
[20] I.S. Hsu, and T.K. Truong; and L.J. Deutsch, and I.S. Reed. “A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases,” IEEE Transactions on Computers, Vol. 37, pp. 735–739, June 1998.
[21] K. Yano, and T. Yamanaka, and T. Nishida, and M. Saitoh, and K. Shimohigashi, and A. Shimizu, “A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic,” Proceedings of the IEEE 1989 Custom Integrated Circuits Conference, pp. 10.4/1-10.4/4, May 1989.
[22] M. Suzuki, and N. Ohkubo, and T. Shinbo, and T. Yamanaka, and A. Shimizu, and K. Sasaki, and Y. Nakagome, “A 1.5-ns 32-b CMOS ALU in double pass-transistor logic,” IEEE Journal of Solid-State Circuits, Vol. 28, pp. 1145-1151, Nov 1993.