臺灣博碩士論文加值系統

本晶片利用回授控制機制的方式來實現具頻率輸出之可調整動態範圍的CMOS影像感測器。整體架構包含 的像素陣列、行處理電路、行及列的移位暫存器、偏壓電路、數位緩衝器。而行處理電路中包括比較器、D型閂鎖器、八位元計數器以及記憶體。本架構的特色在於能夠藉由改變比較器中的參考電壓或是每一列像素的讀取時間來調整影像的動態範圍。模擬結果顯示出此影像感測器原先的動態範圍為78dB，在高照度時藉由調整過後可達到100dB，總共改善了22dB。
像素的部份採用類似於傳統3T架構的像素，但額外增加了兩顆電晶體，分別用來改善像素的轉換增益以及提高讀取時的精準度。而晶片的數位控制訊號是經由FPGA產生，除了在測試時具有更大的彈性之外，還可以降低設計電路時的複雜度。
本晶片使用台積電 2P4M 3.3V混合訊號製程，晶片面積 ，像素面積 ，其內部使用N-well/P-sub接面的光二極體，且填充率達38.6%。

This test chip is used feedback mechanism to realize a frequency output CMOS image sensor with adaptive dynamic range. The full chip consists of 64 64 pixel arrays, column processing circuits, column and row shift register, biasing circuit and digital buffer. And column processing circuits comprise comparator, D flip-flop, an eight bits counter and memory. This structure characters the adaptive dynamic range by adjusting the reference voltage of comparator or readout time of one-row pixel. Simulation results show that the dynamic range of the sensor is 78dB originally and achieves to 100dB in high illumination after adjusting parameters. It can extend dynamic range of 22dB.
This sensor adopts 3T-like pixel which has extra two transistors to improve the conversion gain of pixel and achieve higher precision in readout. Furthermore, the digital control signal is generated by FPGA. It not only has larger flexibility in test but also reduce the circuit complexity.
The test chip is fabricated in TSMC 0.35μm 2P4M 3.3V mixed-mode process and occupies the area of 1.684×1.641 mm2. Each pixel adopts N-well/P-sub photodiode and measures the area of and fill-factor of 38.6%.

第一章 簡介 1
1.1 研究動機 1
1.2 論文架構 2
第二章 文獻回顧 3
2.1 感光元件的基本原理 3
2.2 CMOS影像感測器參數介紹 6
2.3 像素感測器 9
2.4 相關二次取樣電路 14
2.5 行與行的定態雜訊消除電路 16
第三章 電路設計 18
3.1 系統架構與運作 18
3.2 像素陣列 23
3.3 行處理電路 26
3.4 移位暫存器 41
3.5 偏壓電路 44
3.6 系統模擬結果 45
3.7 全晶片佈局 49
第四章 晶片量測 53
4.1 測試環境 53
4.2 測試板設計 55
第五章 結論與未來改善 59
5.1 結論 59
5.2 未來改善 59
參考文獻 61
自述 63

[1]H.-S. Wong, “Technology and device scaling
considerations for CMOS imagers,”IEEE Trans. Electron Devices, vol. 43, no. 12, pp. 2131–2142, Dec. 1996.
[2]E. R. Fossum, “CMOS image sensors: Electronic camera-on-a-chip,” IEEE Trans. Electron Devices, vol. 44, no. 10, pp. 1689–1698, Oct. 1997.
[3]A. El Gamal, “Trends in CMOS image sensor technology and design,” in IEDM Tech. Dig., 2002, pp. 805–808.
[4]H. Rhodes, G. Agranov, C. Hong, U. Boettiger, R. Mauritzson, J. Ladd, I. Karasev, J. McKee, E. Jenkins, W. Quinlin, I. Patrick, J. Li, X. Fan, R. Panicacci, S. Smith, C. Mouli, and J. Bruce, “CMOS imager technology shrinks and image performance,” in Proc. IEEE Workshop Microelectron. Electron Devices, Apr. 2004, pp. 7–18.
[5]S.-G. Wuu, H.-C. Chien, D.-N. Yaung, C.-H. Tseng, C. S. Wang, C.-K. Chang, and Y.-K. Hsaio, “A high performance active pixel sensor with 0.18 μm CMOS color imager technology,” in IEDM Tech. Dig., Dec. 2001, pp. 555–558.
[6]A. El. Gamel, “Image Sensors and Digital Cameras,“ course handout, Standford University, 2001.
[7]C. C. Enz and G. C. Temes, “Circuit Techniques for Reducing the Effects of Op- Amp Imperfections: Auto-Zeroing, Correlated Double Sampling and Chopper Stabilization,” Proceedings of IEEE, vol. 84, no. 11, pp.1584–1614, Nov. 1996.
[8]S. K. Mendis, , S. E. Kemeny, R. C. Gee, B. Pain, C. O. Staller, Q. Kim, “CMOS Active Pixel Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid-State Circuits, vol. 32, no. 2, 1997
[9]Decker, S., McGrath, R., Brehmer, K., Sodini, C., “A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output,” Solid-State Circuits Conference, 1998 Digest of Technical Papers. 45th ISSCC 1998 IEEE International, 5-7, Page(s):176 - 177, 433, Feb. 1998.
[10]G. M. Yin, F. Op’t Eynde, and W. Sansen, “A High-Speed CMOS Comparator with 8-b Resolution,” IEEE Journal of Solid-State Circuits, vol. 27, no. 2, Feb. 1992
[11]L. Luh, J. Choma Jr., J. Draper, “ A High-Speed High-Resolution CMOS Current Comparator,” Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99, vol. 1, pp. 303-306, 1999
[12]B. Razavi, “Principles of Data Conversion System Design, ” IEEE Press
[13]Stuart K. Tewksbury and Joe E. Brewer, Series Editiors, “ CMOS Circuit Design, Layout, and Simulation”, IEEE Press Series on Microelectronic Systems