臺灣博碩士論文加值系統

當浮動式閘極結構之快閃記憶體無法滿足元件微縮的發展時，SONOS-type是取代浮動閘極結構的熱門候選者之一。但是，以氮化矽為電荷儲存層之SONOS快閃記憶體發展到次微米以下時並無法再以降低穿隧氧化層的方式來提高寫入速度，故有很多文獻將以高介電係數材料來取代氮化矽來當作電荷儲存層，但此時面臨到的考驗將會是電荷保持力的持久度。
本實驗將利用不同高介電係數材料以及氮化矽將以堆疊的方式堆疊出電荷儲存層，研究主要是利用不同材料具有不同的特性，配合堆疊式的結構，藉著電荷陷阱密度的多寡、材料結晶溫度的高低、能隙大小的改變、K值影響分壓的不同、陷阱能階的深淺等種種原因，利用能帶工程堆疊出最恰當的電荷儲存層。
由實驗結果得知，不同Hf/Al組成比堆疊出的電荷儲存層，以先疊Al成分較高的，再疊Al成分低的，這樣的堆疊形成電荷儲存層會有較佳的元件效能。以能隙觀點來看，先疊能隙較大的組成比(Hf/Al=1/4)，再疊能隙較小的組成比(HfO2)，可使得元件效能提升。
同樣的，堆疊式電荷儲存層結構採用先疊氮化矽，再疊高介電係數材料HfO2可使得元件效能提升。實驗F-N穿隧寫入機制將使用F-N Tunneling與Trap-assisted Tunneling來加以說明。

誌謝 I
摘要 III
目錄 IV
圖目錄 VI
表目錄 VI
第一章 序論 1
1.1 前言 1
1.2快閃記憶體面臨問題 2
1.3 SONOS快閃記憶體的結構及其優點與面臨問題 2
1.4 High-K 材料應用在快閃記憶體的儲存層上 5
1.5 各章摘要 8
第二章 快閃記憶體元件操作方法 15
2.1寫入與擦拭方法 15
2.1.1通道熱電子注入寫入 15
2.1.2 F-N穿隧寫入 16
2.1.3 F-N穿隧擦拭 17
2.2耐力 18
2.3干擾 19
2.4電荷保持 20
第三章 實驗規劃及元件製程 30
3.1 實驗規劃 30
3.2 電容元件製程 31
3.2.1 電容前段製程 31
3.2.2 成長穿隧氧化層 32
3.2.3 沈積電荷儲存層及上氧化層 32
3.2.4後段製程 33
第四章 高介電材料堆疊應用在穿隧氧化層及電荷儲存層對電荷陷阱式快閃記憶體元件的影響 39
4.1研究背景與目的 39
4.2實驗規劃及製程 40
4.3 實驗結果與討論 42
4.3.1堆疊式穿遂氧化層效應 42
4.3.2 堆疊式電荷儲存層效應 45
4.4結論 51
第五章 各種組成比Hf/Al形成HfxAlyO 運用在電荷儲存層對於電荷陷阱式快閃記憶體之特性研究 70
5.1 實驗背景與目的 70
5.2 實驗規劃與製程 71
5.3 實驗結果與討論 72
5.3.1 單層不同組成比的HfxAlyO電荷儲存層之比較 73
5.3.2 堆疊雙層不同組成比的HfxAlyO形成電荷儲存層對電荷陷阱式快閃記憶體操作特性研究 76
5.4 結論 82
第六章 Si3N4搭配高介電材料HfO2的電荷儲存層堆疊運用在電荷陷阱式快閃記憶體 101
6.1研究背景與目的 101
6.2實驗規劃及製程 102
6.3材料Si3N4搭配高介電材料HfO2的堆疊運用在電荷陷阱式快閃記憶體中 103
6.4結論 106
第七章 結論與建議 118
7-1結論 118
7-2建議 119
參考文獻 120

[1] Min She, “Semiconductor Flash Memory Scaling”, 2003
[2] 薛富元,“由模擬來探討Floating Gate Memory及SONOS元件微小化之極限”,國立清華大學電子工程研究所
[3] Corporation Flash Memory Group,"Technology Scaling
Impact on NOR and NAND Flash Memories and Their Applications" IEEE Oct. 2006 Page(s):697 - 700
[4] Yan-Ny Tan, et al., ”Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage Layer”, IEEE Transactions on Electron Device ,Vol.51, No.7,JULY, 2004. Page(s):1143 - 1147
[5] Moon Sig Joo, et al., ”Dependence of Chemical Composition Ratio on Electrical Properties of HfO2-Al2O3 Gate Dielectric”, Jpn. J. Appl. Phys., No.3A, Pl220-l222, MARCH 2003.
[6] W. J. Zhu, et al., ”Effect of Al Inclusion in HfO2 on the Physical and electrical properties of the dielectrics”, IEEE Electron Electron Device Letters, Vol.23, No.11, 2002 Page(s):649 - 651.
[7] J. Petry, et al., ”The band structure of ALCVD AlZr and AlHf oxides as measured by XPS”, Materials Science and Engineering, 2004.
[8] Yan Ny Tan " Hafnium Aluminum Oxide as Charge Storage and Blocking-Oxide Layers in SONOS-Type Nonvolatile Memory for High-Speed Operation" IEEE Transactions on Electron Devices, VOL. 53, NO. 4, APRIL 2006 Page(s):654 - 662
[9] Hang-Ting Lue, et al., ”BE-SONOS A bandgap engineered SONOS with excellent performance and reliability”, IEEE International Electron Devices Meeting, 5-7 Dec 2005 Page(s):547 - 550
[10] Jan Van Houdt, et al., “High-k materials for nonvolatile memory applications” ,IEEE Physics Symposium, April 17-21, 2005 Page(s):234 - 239
[11] Jiankang Bu, et al., “Retention reliability enhanced SONOS NVSM with scaled programming voltage”, IEEE Aerospace Conference paper, Vol.5, P5-2383 5-2390,2001
[12] Marvin H. White, et al., “A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol.20, No.2, JUNE 1997. IEEE JNL June 1997 Page(s):190 - 195
[13] W. J. Tsai, et al., “Data retention behavior of a SONOS type two-bit storage flash memory cell”, IEEE International Electron Devices Meeting, 2001 Page(s):32.6.1 - 32.6.4
[14] K. Tamer San, et al., “Effects of erase source bias on Flash EPROM device reliability”, IEEE Transactions on Electron Devices , Vol.42, No.1, JANUARY 1995 Page(s):150 - 159
[15] Verma, et al., ”Reliability Performance of ETOX Based Flash Memory”, International Reliability Physics Symp, P.158, 1998
[16] Haddad, et al., ”Degradation Due to Hole Trapping in Flash Memory Cells”, IEEE Electron Dev. Lett., Vol.10, No3, P.117, Mar. 1989.
[17] Adam Brand, et al., ”Novel Read Distub Failure Mechanism Induced by Flash Cycling”, International Reliability Physics Symp., P.127, 1993.
[18] Ping-Hung Tsai,et al.,”Novel SONOS-Type Nonvolatile Memory Device With Optimal Al Doping in HfAlO Charge-Trapping Layer” IEEE Electron Device Letters,VOL.29,NO.3,MARCH 2008 Page(s):265 - 268
[19] Robert F. Steimle,et al., ”Hybrid Silicon Nanocrystal Silicon Nitride Dynamic Random Access Memory” Dec. 2003 Page(s):335 – 340
[20] Naoto Umezawa,et al., ” The Role of Nitrogen Incorporation in Hf-based High-k Dielectrics: Reduction in Electron Charge Traps”, IEEE Proceedings of ESSDERC, France, 2005,p201.
[21] Gang Zhang, et al”Novel ZrO2/Si3N4 Dual Charge Layer to Form Step-Up Potential Wells for Highly Reliable Multi-Level Cell Application” ,IEEE IEDM 10-12 Dec. 2007 Page(s):83 - 86
[22] Y.Q.Wang,et al., “Fast erasing and highly reliable MONOS type memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack” IEEE IEDM 11-13 Dec. 2006 Page(s):1 - 4
[23] ZongLiang Huo,et al., “Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory” 2007 Symposium on VLSI Technology Digest of Technical Papers 12-14 June 2007 Page(s):138 - 139
[24] Tung-Sheng Chen,et al.,”Performance Improvement of SONOS Memory by Bandgap Engineering of Charge-Trapping Layer” 2004IEEE JNL April 2004 Page(s):205 - 207
[25] J.Buckley,et al.,”In-depth Investigation of Hf-based High-k Dielectrics as Storage Layer of Charge–Trap NVMs” IEEE IEDM 11-13 Dec. 2006 Page(s):1 - 4