臺灣博碩士論文加值系統

隨著半導體科技的進步以及元件尺寸不斷地微縮，ESD所造成的影響越來越趨嚴重，要如何讓高壓元器件在嚴苛的操作環境下還能擁有良好排放大電流的能力是目前所致力的目標。論文架構第一章為研究動機，說明此篇論文的研究方向；第二章為ESD相關原理介紹，也提到了本文中量測所用到的傳輸線脈衝系統；第三章為介紹文中用到的所有元件架構；而第四章則是所有元件的量測數據，並將量測結果進行討論與分析。
本論文針對TSMC 0.25 µm製程60V高壓MOSFET元件進行一系列的結構以及佈局方式的調變，並透過TLP系統所量測後的結果來探討高壓元件結構對ESD能力之影響。元件佈局結構上分為四個部分：第一部分以傳統條狀nLDMOS+SCR為主體，驗證陽極端(汲極端)P+擴散區植入位置及SCG (Source-Contact-to-Gate)參數的調變對ESD能力的影響。第二部分以田狀nLDMOS+SCR為主體，將第一部分提到的傳統nLDMOS+SCR結構以不同的田狀nLDMOS+SCR型式佈局，並改變SCG值、閘極端相連與否的方式、寄生SCR的陽極端(汲極端)與陰極端(源極端)的調變以及田狀-II佈局方式來互相比較。第三部分是以傳統條狀pLDMOS+SCR為主體，改變陽極端(汲極端)N+植入位置來探討其靜電防護能力。最後一部分則是以田狀pLDMOS+SCR為主體，以田狀的pLDMOS+SCR佈局型式與傳統條狀進行比較，同時也調變陽極端(汲極端)和陰極端(源極端)來探討其對ESD能力的影響。透過以上結構的調變以及探討，希望可以得到一個擁有高抗ESD能力的高壓元器件。

With the semiconductor technology evolving and scaling, electrostatic discharge (ESD) events make ICs damage seriously. So, how to have a high-voltage (HV) device with an effective ESD capability in the harsh enviroment is a very important issue. In this thesis, Chapter 1 is the motivation and Chapter 2 introduces the principles of ESD-related, which contains an introduction of TLP measurement system. All the proposed components have been introduced and measured in Chapter 3 and 4, respectively. Then, Chapter 5 is a conclusion.
A TSMC 0.25 µm 60 V process technology will be used in this thesis, the systematic structures with different layout are proposed to explore the influence of experimental result on the snapbackp parameters of components has been investigation by a TLP measurement system. Component layout architecures can be classified into four categories, the first one is the stripe-type of nLDMOS+SCR for the benchmark, including the verification of P+ implant location of anode-side and SCG values modulation of an nLDMOS+SCR, respectively. Second, the nLDMOS+SCR stuctures are proposed to compare the ESD capability with waffle-type layout, SCG values modulation, cathode-side and anode-side modulation and waffle-type-II layout. In the third part, a stripe-type of pLDMOS+SCR is used to evaluated the anti-ESD roubustness by modulated the N+ implant location of the anode-side. The final categorie is waffle-type pLDMOS+SCR components, including the verification of cathode-side and anode-side modulations. Eventually, hope to get an HV device with good ESD capability through the experimental details in this thesis.

致謝 1
目錄 2
圖目錄 5
表目錄 13
摘要 15
Abstract 16
第一章 概論 17
1.1 研究動機 17
1.1.1 高壓元件相關應用 17
1.2 研究方向 19
1.3 論文架構 19
第二章 ESD元件相關原理 20
2.1 不均勻導通現象 20
2.2 ESD元件介紹 21
2.2.1 高壓N型橫向擴散金氧半場效電晶體 (HV-nLDMOS) 21
2.2.2 高壓矽控整流器 (Silicon-Controlled Rectifier) 22
2.3 傳輸線脈衝量測系統 23
第三章 元件佈局設計 25
3.1 高壓nLDMOS+SCR結構 25
3.1.1 傳統條狀nLDMOS+SCR佈局型式 25
3.1.1.1 陽極端(汲極端)P+植入位置調變之驗證 25
3.1.2 田狀nLDMOS+SCR佈局型式 28
3.1.2.1 陽極端(汲極端)調變 30
3.1.2.2 陰極端(源極端)調變 34
3.1.2.3 陰極端(源極端)/陽極端(汲極端)調變 37
3.1.3 田狀-II高壓 nLDMOS+SCR佈局型式 43
3.1.3.1 陰極端(源極端)調變 43
3.2 高壓pLDMOS+SCR結構 44
3.2.1 傳統條狀pLDMOS+SCR佈局型式 44
3.2.1.1 陽極端(汲極端)N+植入位置調變之驗證 44
3.2.2 田狀pLDMOS+SCR佈局型式 48
3.2.2.1 陽極端(汲極端)調變 50
3.2.2.2 陰極端(源極端)調變 54
3.2.2.3 陰極端(源極端)/陽極端(汲極端)調變 56
第四章 量測結果與討論 61
4.1 高壓nLDMOS+SCR結構 61
4.1.1 陽極端(汲極端)P+植入位置與SCG值調變之驗證 (102D梯次) 61
4.1.2 田狀nLDMOS+SCR佈局型式驗證 (102C梯次) 64
4.1.3 田狀高壓nLDMOS+SCR陽極端(汲極端)調變之驗證 67
4.1.3.1 閘極不相連(w/o gate-connected)之佈局型式 (102C梯次) 67
4.1.3.2 閘極相連(w/i gate-connected)之佈局型式 (103A梯次) 73
4.1.4 田狀高壓nLDMOS+SCR陰極端(源極端)調變之驗證 79
4.1.4.1 閘極不相連(w/o gate-connected)之佈局型式 (102C梯次) 79
4.1.4.2 閘極相連(w/i gate-connected)之佈局型式 (103A梯次) 85
4.1.5 田狀高壓nLDMOS+SCR陰極端(源極端)/陽極端(汲極端)調變之驗證 89
4.1.5.1 閘極不相連(w/o gate-connected)之佈局型式 (102C梯次) 89
4.1.5.2 閘極相連(w/i gate-connected)之佈局型式 (103A梯次) 95
4.1.6 田狀-II 高壓nLDMOS+SCR佈局結構 101
4.2 高壓pLDMOS+SCR結構 109
4.2.1 陽極端(汲極端)N+植入位置調變之驗證 (102D梯次) 109
4.2.2 田狀pLDMOS+SCR佈局型式驗證 (102D梯次) 112
4.2.3 田狀pLDMOS+SCR陽極端(汲極端)調變之驗證 (102D梯次) 114
4.2.4 田狀pLDMOS+SCR陰極端(源極端)調變之驗證 (102D梯次) 120
4.2.5 田狀pLDMOS+SCR陰極端(源極端)/陽極端(汲極端)調變之驗證 (102D梯次) 125
第五章 結論與未來展望 130
參考文獻 132
晶片下線紀錄 136
研究成果 140
A. 期刊論文 140
B. 研討會論文 141

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