臺灣博碩士論文加值系統

製造測試是晶片下線之後的一個重要環節，對於效能及面積要求極嚴的處理器，軟體式自我測試方案可以大幅減少測試電路所佔用的電晶體數，使得晶片得以在時脈、良率上都有更大的調整空間。對於在單一晶片上整合兩個以上處理器的多核心系統，上述的優點將會更加的被凸顯，若是能將原本針對單核心系統研發完成的軟體式自我測試程式，藉由增加在多核心平台上所需要的協調機制，使其可以同樣的在多核心平台上執行，必然可以提供多核心晶片在生產測試流程上的重大變革。
本論文中，我們探討了多核心系統的軟體式測試方法，並分別提出透過軟體及硬體的支援來使用原本單核心系統測試程式於多核心系統。將其分別套用到所提出的單晶片多核心系統。實驗結果顯示不管是透過軟體或硬體的機制，將原本針對單核心系統所發展的軟體自我測試程式應用到多核心系統都是相當可行的。

Manufacturing testing is an important stage after the tape-out of a chip. Software-based self-testing (SBST) is a promising methodology for processor which has strict considerations in performance and area. If we can apply well-developed software-based self-testing program to a multi-core system which uses the same processor as in a single-core system, testing development time for the multi-core system can be greatly shortened. In this thesis, we address the SBST issues in multi-core systems and propose a methodology that applies single-core software-based self-testing program to the multi-core system. Our experimental results demonstrate the feasibility of the proposed SBST methodology for a homogeneous multi-core system.

摘要 I
第一章 序論 1
第一節 研究動機 1
第二節 研究貢獻 2
第三節 內容編排 2
第二章 背景知識與相關文獻探討 3
第一節 單核心處理器的測試 3
第二節 一套發展完善的軟體式自我測試方案 4
第三節 多處理器系統及其分類 7
第四節 多處理器系統的軟體式自我測試流程 8
第五節 相關研究 10
第三章 所提出的軟體式自我測試方案 13
第一節 透過軟體的修改 13
同步問題 13
系統是否已有正確(fault-free)的處理器 15
診斷問題 16
第二節 測試程式同步關鍵區段(Test Program Synchronization Section) 21
測試程式同步區段的位置 22
使用測試程式同步區段的議題 23
第三節 利用Design for Test硬體的增加 24
第四節 測試同步單元(Test Synchronization Unit) 25
測試監控器(Test Monitor) 27
測試仲裁器(Test Arbiter) 28
測試控制器(Test Controller) 29
使用測試同步單元的議題 32
第四章 實驗的環境與結果分析 33
第一節 對稱式的單晶片多核心處理器系統 33
第二節 實驗步驟與工具 33
MLA SBST及其修改 34
邏輯模擬與錯誤模擬流程 36
合成的方法 37
第三節 使用測試程式同步區段 38
第四節 使用測試同步單元 39
測試同步單元的合成結果 39
使用測試同步單元的測試結果 39
第五章 結論與未來展望 41
第一節 結論 41
第二節 未來的展望 42
參考資料 43

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