臺灣博碩士論文加值系統

一元化代工服務（統包）在今日顯得日益重要，主要是因為它可以用來幫助積體電路設計公司所推出的新產品，在短時間內製造完成以便即早來搶奪市場佔有率。世界前三大晶圓製造廠─台灣積體電路公司，聯華電子公司以及特許半導體─全都有替他們的顧客提供此類的服務。雖然一元化代工服務能夠為這些積體電路設計公司提供較佳的服務，但是大量且煩人的作業卻因此移到這些晶圓製造廠上。他們必須以達交來滿足顧客，因此晶圓製造廠需要一個監控一元化代工服務訂單加工時間的機制來保護交期表現。
在本論文中，我們利用「限制理論」[6]與「關鍵鏈專案管理」[7]的觀念來建構半導體供應鏈模型與架構。我們應用「關鍵鏈專案管理」，其主要目的在於確保訂單能夠準時達交。然而「關鍵鏈專案管理」是否能夠套用在半導體一元化代工服務是我們首要研究的問題。「關鍵鏈專案管理」裡有兩項基本的觀念：「專案緩衝」與「緩衝管理」。前者可用來計算交期而後者當成監控的機制。「專案緩衝」對交期表現有很大的影響。所以去驗證「專案緩衝」的計算是否合理也是必須的。同樣地，Dr. Goldratt 隨意地將專案緩衝切成三等分也被許多學者質疑，因以我們也必須要驗證這一點。
我們以新竹科學園區一家知名半導體廠商的資料來作為研究的個案。我們以eM-Plant TM [43]來設計模擬實驗，並且驗證了(1)在我們的個案中，專案緩衝的計算可能是不正確的但是當緩衝管理加上Critical Ratio (CR)作為第二層判斷時，運作效果十分良好(2)我們所提出的方法，CCPM3+CR，跟CR相較之下，在同樣的情境之下有較優異的達交率(3)驗證了Dr. Goldratt隨意地將「專案緩衝」切成三等分是合理且可行的(4)當我們用FIFO所得到的平均加工時間做為交期的基準時。CCPM3+CR比CR得到較高的達交率與產出。

Nowadays, the one-stop shopping turnkey service, which facilitates time to market and helps grab the market share, is more important to the IC design houses. Although it may provide better services to IC design houses, laboring tasks are therefore shifting to those FABs. On time delivery is one of the key performance indices of turnkey services. Therefore, a mechanism to control cycle time of turnkey service order to protect due-date performance is necessary.
We present a semiconductor supply chain model constructed under the concept of Theory Of Constraints (TOC) [6] as well as Critical Chain Project Management (CCPM) [7]. The objective of CCPM intends to improve on time delivery [7]. However, whether CCPM is applicable for the semiconductor turnkey services deserves to be studied. There are basically two major concepts in CCPM. They are “project buffer” and “buffer management.” The former is utilized to calculate the due date while the latter serves as the monitoring and control mechanism. The project buffer strongly influences the due-date performance. To verify the feasibility of the estimate of project buffer proposed by Dr. Goldratt is necessary. In the meanwhile, Dr. Goldratt’s arbitrarily divided the project buffer into three equal zones for buffer management [7], which has been criticized by many researchers, needs to be justified, too.
A case with real world data from a foundry FAB in Hsinchu Science-Based Industrial Park in Taiwan is employed. We conduct experimental simulation using eM-Plant TM [43] and demonstrate that (1) the estimate of project buffer may be improper in this typical case while buffer management works well with critical ratio (CR) as a tie-break rule, (2) the concept to divide project buffer into 3 equal zones (CCPM3) is reasonable and workable in this typical case, (3) CCPM3+CR, our proposed method, yields superior average on-time-delivery percentage (AOTDP) than the legacy dispatching rule, CR, does, and (4) due date in this study is designated based on the average cycle time obtained with first in first out (FIFO) where 50% of AOTDP will be achieved. CCPM3+CR yields higher AOTDP and higher throughput (TPT) than CR does in this typical case.

中文摘要 I
ABSTRACT II
ACKNOWLEDGEMENTS III
CONTENTS IV
LIST OF FIGURES VI
LIST OF TABLE VIII
CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND AND MOTIVATION 1
1.2 OBJECTIVES 3
1.3 RESEARCH SCOPE 5
1.4 FRAMEWORK OF STUDY 6
CHAPTER 2 LITERATURE REVIEW 7
2.1 TURNKEY SERVICE 7
2.1.1 Turnkey Service Managed by FAB 7
2.1.2 Turnkey Service Managed by Assembly and Final Testing 8
2.2 MANUFACTURING CHARACTERISTICS OF THE SEMICONDUCTOR INDUSTRY 10
2.2.1 Manufacturing Characteristics of the IC Design House 11
2.2.2 Manufacturing Characteristics of the FAB 13
2.2.3 Manufacturing Characteristics of the Chip Probing (CP) 15
2.2.4 Manufacturing Characteristics of the Die Bank (DB) 17
2.2.5 Manufacturing Characteristics of the Assembly/Packaging (AS) 18
2.2.6 Manufacturing Characteristics of the Final Testing (FT) 19
2.3 TOC’S PROJECT MANAGEMENT-CRITICAL CHAIN PROJECT MANAGEMENT 20
2.3.1 TOC (Theory of Constraints) 20
2.3.2 Critical Chain Project Management (CCPM) 20
2.3.3 Buffer Management 22
2.3.4 Applications of CCPM 22
2.5 SUMMARY OF LITERATURE REVIEW 25
CHAPTER 3 METHODOLOGY 26
3.1 KEY PERFORMANCE INDICATORS (KPI) 26
3.1.1 Quantitative Metrics Related to Cycle Time 28
3.2 DEFINITION OF ON TIME DELIVERY PERCENTAGE 31
3.3 ESTIMATES OF PROJECT AND FEEDING BUFFERS 32
3.3.1 The Cut and Paste Method 32
3.3.2 The Root-Square-Error (RSE) Method 34
3.3.3 Revised RSE Method 36
CHAPTER 4 CASE STUDY AND SIMULATIONS 39
4.1 STEP ONE: DEFINE THE SCENARIO 40
4.1.1 Environments of the Case Study - Intricate Network Scenario 40
4.1.2 Local Environments 41
4.1.3 Releasing Policy - CONWIP (CONstant Work In Process) 41
4.1.4 Dispatching Rule — Priorities and Critical Ratio (CR) 42
4.1.5 Definition of Layer within FAB 43
4.1.6 Model Assumptions 44
4.2 STEP TWO: FIT HISTORICAL DATA INTO OUR MODEL AND CHECK THE FEASIBILITY OF CCPM 46
4.3 STEP THREE: DESIGNATE AND THE CONFIRM DUE DATE 48
4.4 STEP FOUR: COMPARE THE PERFORMANCE TO LEGACY SYSTEM (CR) 51
4.5 STEP FIVE: CONSTRUCT MONITORING MECHANISM 55
CHAPTER 5 CONCLUSION AND FUTURE STUDY 57
5.1 CONCLUSION 57
5.2 DIRECTIONS OF FUTURE STUDY 58
REFERENCE: 59
APPENDIX 1 ILLUSTRATION OF SIMULATION MODEL 63
APPENDIX 2 HISTORICAL CYCLE TIME DATA 68
APPENDIX 3 FITTED CYCLE TIME DATA 69
APPENDIX 4 DETAILED REPORT OF FITTED DATA 73
APPENDIX 5 DETAILED REPORT OF CONFIRMATION 76
APPENDIX 6 DETAILED REPORT OF COMPARISON 79

[1] “Design Implementation Services,” http://www.tsmc.com.tw/index.html
[2] J. K. Lu, S. T. Hsieh, C. C. Feng, H. W. Hsu,“B2B in TSMC Turnkey Services,” Semiconductor Manufacturing Symposium, 2001 IEEE International, 2001, pp 41-44
[3] E. Elam and A. Hinnawi, “UMC serves system design house requirements via new ASICplus program,” http://www.umc.com/english/news/20000201.asp
[4] http://www.charteredsemi.com/index.htm
[5] PMI Standards Committee, “A Guide to the Project Management Body of Knowledge,” Project Management Institute, 1996
[6] E. M. Goldratt and J. Cox, “The Goal: A Process of Ongoing Improvement,” New York: The North River Press, 1986
[7] E. M. Goldratt, “Critical Chain,” New York: The North River Press, 1997
[8] J. D. C. Little, “A Proof of the Queuing Formula: L= W,” Operations Research, Vol. 9, 1961, pp 383-387
[9] Y. H. Lee, “Supply Chain Model for the semiconductor Industry of Global Market,” Journal of Systems Integration, 10, 2001, pp189-206
[10] W. C. Wu, “A Study of Turnkey Service for Semiconductor,” Master Thesis, Department of Industrial Engineering and Management, National Chiao Tung University, HsinChu, Taiwan, ROC, 2001
[11] P. H. Chen, “A Production Resource Requirement Planning for IC Design House,” Master Thesis, Department of Industrial Engineering and Engineering Management, National Tsing Hua University, Hsinchu, Taiwan, ROC, 1997
[12] http://e-www.motorola.com/, “Motorola Inc.”
[13] S. Jain, C. C. Lim, B. P. Gan, and Y. H. Low, “Criticality of Detailed Modeling in Semiconductor Supply Chain Simulation,” Proceedings of the 1999 Winter Simulation Conference, 1999, pp888-896
[14] S. J. Turner, W. Cai, and B. P. Gan, “Adapting a Supply-chain Simulation for HLA,” Proceedings of Fourth 2000 IEEE International Workshop on Distributed Simulation and Real-Time Applications, 2000, pp71-78
[15] Y. C. Lu, “A Production Planning System for IC Design House,” Master Thesis, Department of Industrial Engineering and Engineering Management, National Tsing Hua University, Hsinchu, Taiwan, ROC, 1999
[16] B. S. Chen, “A Framework of Production Planning and Control for IC Design House,” Master Thesis, Department of Industrial Engineering and Engineering Management, National Tsing Hua University, Hsinchu, Taiwan, ROC, 1998
[17] J. W. Chen, “A Study of Lot-Tracking System for IC Design Houses,” Master Thesis, Department of Industrial Engineering and Management, National Chiao Tung University, Hsinchu, Taiwan, ROC, 2000
[18] R. Uzsoy, C.Y. Lee and L. A. Martin-vega, “A Review of Production Planning And Scheduling Models In The Semiconductor Industry Part I: System Characteristics, Performance Evaluation And Production Planning,” IIE Transactions, Vol. 24, No. 4, 1992, pp47-60
[19] H. W. Hwang, “The Design of Production Activity Control for Wafer Fabrication Factory,” Master Thesis, Department of Industrial Engineering and Management, National Chiao Tung University, Hsinchu, Taiwan, ROC, 1995
[20] I. Duenyas, J. W. Fowler, and L. W. Schruben, “Planning and Scheduling in Japanese Semiconductor Manufacturing,” Journal of Manufacturing Systems, Vol. 13, No. 5, 1994, pp323-332
[21] R. Sturm, F. Frauenhoffer, J. Dorner, O. Kirschenhofer, and T. Reisinger, “Advanced WIP control for Make-to-Order Wafer Fabrication,” Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI, 1999, pp31-36
[22] Y. H. Lee, B. K. Lee, and B. Jeong, “Multi-objective production scheduling of probe process in semiconductor manufacturing,” Production Planning & Control, Vol. 11, No. 7, 2000, pp660-669
[23] S. V. Murty and J. W. Bienvenu, “Global Planning at Harris Semiconductor,” 1995 International Symposium on Semiconductor Manufacturing, 1995, pp18-23
[24] R. C. Leachman, “Modeling Techniques for Automated Production Planning in the Semiconductor Industry,” Optimization in Industry: Mathematical Programming and Modeling Techniques in Practice, Chichester, UK, John Wiley & Sons, 1993, pp1-30
[25] C. Liu, “A Modular Production Planning System for Semiconductor Manufacturing,” Ph.D. Dissertation, Department of Industrial Engineering and Operations Research, University of California, Berkeley, Berkeley, CA, 1992
[26] I. M. Ovacik and W. Weng, “A Framework for Supply Chain Management in Semiconductor Manufacturing Industry,” Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1995, pp47-50
[27] J. L. Bouff, “Semiconductor manufacturing: A supply chain management perspective,” Conference on Global Supply Chain Management, Singapore, 1997
[28] A. I. Sivakumar and C. S. Chong, “A simulation based analysis of cycle time distribution, and throughput in semiconductor backend manufacturing,” Computer in Industry, Vol. 45, 2001, pp59-78
[29] T. R. Chen and T. C. Hsia, “Scheduling for IC Sort and Test Facilities with Precedence Constraints via Lagrangian Relaxation,” Journal of Manufacturing Systems, Vol. 16, No. 2, 1997, pp117-128
[30] L. P. Leach, “Critical Chain Project Management Improves Project Performance,” Project Management Journal, Vol. 30, No. 2, 1999, pp39-51
[31] Herman Steyn, “An investigation into the fundamentals of critical chain project scheduling,” International Journal of Project Management, Vol. 19, 2000, pp363-369
[32] http://www.pdinstitute.com/, “Project Management Tutorials”
[33] S. C. Cook, “Applying Critical Chain to Improve the Management of Uncertainty in Projects,” Master Thesis, Massachusetts Institute of Technology, MA, 1998
[34] C. D. Hsu, “Studying the short cycle time and the model of the due date control for IC packaging factory,” Master Thesis, Department of Industrial Engineering and Management, National Chiao Tung University, HsinChu, Taiwan, ROC, 1998
[35] S. N. Huang, “Application of the TOC’s Aggregated Buffer to the Due Date Control in the Semiconductor Wafer Fabrication,” Master Thesis, Department of Industrial Engineering and Management, National Chiao Tung University, HsinChu, Taiwan, ROC, 1999
[36] Tim Lister, “Hallucinations at 37,000 Feet,” IEEE Software, Vol. 15, No. 3, 1998, pp105-107
[37] Y. Shou and K. T. Yeo, “Estimation of Project Buffers in Critical Chain Project Management,” Proceedings of the 2000 IEEE International Conference on Management of Innovation and Technology, Vol. 1, 2000, pp162-167
[38] I. Miller and J. E. Freund, “Probability and Statistics for Engineers,” 2nd Edition, New Jersey: Prentice-Hall, 1977, pp169-170
[39] M. L. Spearman, D. L. Woodruff and W. J. Hopp, “CONWIP: a pull alternative to kanban,” International Journal of Production Research, Vol. 28, No.5, 1990, pp879-894
[40] N. G. Pierce and T. Yurtsever, “Value-Based Dispatching for Semiconductor Wafer Fabrication,” 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, 2000, pp245-249
[41] P. McGlynn and M. O''Dea, “How to get predictable Throughput times in a Multiple Product Environment,” 1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, 1997, pp27-30
[42] J. Y. Shieh, “A Study of Dispatching Logic for the Photolithography Area and the Furnace Area in a Wafer Fab,” Master Thesis, Department of Industrial Engineering and Management, National Chiao Tung University, HsinChu, Taiwan, ROC, 1998
[43] http://www.emplant.de/, eM-PlantTM