臺灣博碩士論文加值系統

由於動態可程式邏輯陣列結構具有可預期繞線延遲時間和高速。可程式邏輯陣列結構通常用在數位系統的組合電路和控制電路。但在現今系統晶片化(SOC)的趨勢下，控制電路的複雜性增加，也提高對速度和功率的電路設計要求。雖然最新的Kwang's PLA架構已經被提出來，能有效的降低功率消耗和延遲時間。但這電路需要更複雜和大的面積。
為了解決這問題，提出一個新型低功率可程式邏輯陣列結構基於閘擴散輸入(GDI)。這GDI技術允許數位電路降低功率消耗，傳播延遲和面積。它也維持電路設計的低複雜性。本論文，我們採用GDI技術來修改Kwang's PLA，它使用一個GDI電路來取代Kwang's PLA每一條乘積線的有條件評估電路。為了驗證所提出的可程式邏輯陣列結構，我們使用MCNC可程式邏輯陣列結構標準電路來進行實驗。利用alu2在MCNC標準之0.18微米CMOS技術下，模擬結果顯示所提出的方案跟Kwang's PLA相比較能降低28.1%的電晶體數量、40.6%的功率消耗、15%的延遲時間和49.5%的總功率延遲乘積。

Because of the dynamic PLA structure has predictable routing delay and high speed, the PLA structure is usually built using combinational and sequential circuits in digital systems. But the trend of system on chip (SOC) today, the complexity of the control circuit is increased, and the speed and power circuit design requirements also increased. Although latest Kwang's PLA architecture had been proposed, which can effectively reduce power consumption and delay time, but this circuit is more complex and has a larger area.
In order to solve this problem, a novel low power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows the reduction of power consumption, propagation delay, and area of digital circuits, and it also maintains the low complexity of circuit design. In this thesis, we use the GDI technique to modify Kwang's PLAs in which we use one GDI circuit to replace the conditional evaluation circuit in every product lines. In order to verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform simulations. Simulation results show that the proposed scheme can reduced the number of transistors by 28.1%, power consumption by 40.6%, delay time by 15% and total power delay product (PDP) by 49.5% compared with Kwang’s PLAs which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.

Contents
Chinese Abstract i
English Abstract ii
Acknowledgements iii
Contents iv
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Organization 5
Chapter 2 Low-Power/High-Speed PLA Design 6
2.1 Introduction 6
2.2 Conventional Clock-Delayed PLA 8
2.3 Blair’s PLA 12
2.4 Wang’s PLA 14
2.5 Kwang’s PLA 16
2.6 Summary 19
Chapter 3 The New Design PLA with GDI Scheme 20
3.1 Introduction 20
3.2 The Concept of the GDI Scheme 22
3.3 Using the GDI Technology in Kwang’s PLA 24
Chapter 4 Simulation Results 30
4.1 The Simulation Tool of Design Flow 30
4.2 Post-Simulation by TSMC 0.18μm 1P6M CMOS Technology 31
4.3 Chip Layout 46
Chapter 5 Conclusion 49
Reference 50



List of Figures
Figure 1.1 Aan example of a dynamic PLA with the NOR-NOR structure. 2
Figure 2.1 A conventional 5×8×4 clock-delayed PLA. 10
Figure 2.2 The critical path circuit of conventional clock-delayed PLA. 11
Figure 2.3 The propagation waveforms of conventional clock-delayed PLA. 11
Figure 2.4 The critical path circuit of Blair’s PLA. 13
Figure 2.5 The propagation waveforms of Blair’s PLA. 14
Figure 2.6 The critical path circuit of Wang’s PLA. 15
Figure 2.7 The propagation waveforms of Wang’s PLA. 16
Figure 2.8 The critical path circuit of Kwang’s PLA. 17
Figure 2.9 The propagation waveforms of Kwang’s PLA. 18
Figure 3.1 A GDI cell. 22
Figure 3.2 The critical path circuit of our proposed PLA. 26
Figure 3.3 The propagation waveforms of our proposed PLA. 26
Figure 3.4 Shows the example of our proposed PLA. 28
Figure 3.5 Shows the example of Kwang’s PLA. 29
Figure 4.1 The Monte Carlo analysis method. 31
Figure 4.2 The performance comparison results of various PLA post-simulation at 100MHz. 35
Figure 4.3 The performance comparison results of various PLA post-simulation at 150MHz. 35
Figure 4.4 The performance comparison results of various PLA post-simulation at 250MHz. 36
Figure 4.5 The propagation waveforms of our proposed PLA for the benchmark circuit alu2 simulates at 100MHz. 37
Figure 4.6 The propagation waveforms of the new GDI cell for the benchmark circuit alu2 simulates at 100MHz. (a) Input. (b) Output. 38
Figure 4.7 The propagation waveforms of the new GDI cell for the benchmark circuit alu2 simulates at 150MHz. (a) Input. (b) Output. 38
Figure 4.8 The propagation waveforms of the new GDI cell for the benchmark circuit alu2 simulates at 250MHz. (a) Input. (b) Output. 39
Figure 4.9 The total power dissipation (TPOWRD) of Blair’s PLA for the benchmark circuit alu2 simulates at 250MHz. 40
Figure 4.10 The total power dissipation (TPOWRD) of Wang’s PLA for the benchmark circuit alu2 simulates at 250MHz. 40
Figure 4.11 The total power dissipation (TPOWRD) of Kwang’s PLA for the benchmark circuit alu2 simulates at 250MHz. 41
Figure 4.12 The total power dissipation (TPOWRD) of the proposed PLA for the benchmark circuit alu2 simulates at 250MHz. 41
Figure 4.13 Input of PLA for the benchmark circuit alu2 simulates at 250MHz. 42
Figure 4.14 The propagation waveforms of Wang’s PLA for the benchmark circuit alu2 simulates at 250MHz. 43
Figure 4.15 The propagation waveforms of Kwang’s PLA for the benchmark circuit alu2 simulates at 250MHz. 43
Figure 4.16 The propagation waveforms of our proposed PLA for the benchmark circuit alu2 simulates at 250MHz. 44
Figure 4.17 Output of PLA for the benchmark circuit alu2 simulates at 250MHz. (a)Wang’s PLA. (b) Kwang’s PLA. (c) Our proposed PLA. 45
Figure 4.18 Layout of Blair’s PLA for the benchmark circuit alu2 used the 0.18μm technology. 46
Figure 4.19 Layout of Wang's PLA for the benchmark circuit alu2 used the 0.18μm technology. 47
Figure 4.20 Layout of Kwang's PLA for the benchmark circuit alu2 used the 0.18μm technology. 47
Figure 4.21 Layout of our proposed PLA for the benchmark circuit alu2 used the 0.18μm technology. 48

List of Tables
Table 3.1 Various logic functions of GDI cell. 23
Table 3.2 The output swing of F1 function. 23
Table 3.3 The new GDI cell true table. 25
Table 4.1 The comparison results of the number of transistors of various PLA. 32
Table 4.2 The post-simulation comparison results of power consumption at 100MHz, 150MHz and 250MHz, respectively. (units: mW) 33
Table 4.3 The post-simulation comparison results of delay at 100MHz, 150MHz and 250MHz, respectively. (units: ns) 33
Table 4.4 The post-simulation comparison results of PDP at 100MHz, 150MHz and 250MHz, respectively. (units: pJ) 34

Reference
[1] H. Yamaoka et al, “A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme, ” Proc. ASP-Design Automation Conference, pp. 3-4, Feb. 2001.
[2] Oh J. Kwang-Il, Kim. Lee-Sup Kim, “A high performance low power dynamic PLA with conditional evaluation scheme,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 881-884, May 2004.
[3] G. M. Blair, “PLA design for single-clock CMOS,” IEEE Journal of Solid-State Circuits, vol. 27, no. 8, pp. 1211-1213, Aug. 1992.
[4] J. S. Wang, C. R. Chang, and C. Yeh, “Analysis and design of high-speed and low-power CMOS PLAs,” IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1250-1262. Aug. 2001.
[5] N. Weste and K. Eshrahian, Principles of CMOS VLSI Design-A System Perspective, ed. 1, Addison-Wesley, 1985.
[6] Y. B. Dhong and C. P. Tsang, “High speed CMOS POS PLA using predischarged OR array and charge sharing AND array,” IEEE Transactions Circuits and Systems, vol. 39, no. 8, pp. 557-564, Aug. 1992.
[7] C. C. Wang, C. F. Wu, R. T. Hwang, and C. H. Kao, “A Low-Power and High-Speed Dynamic PLA Circuit Configuration for Single-Clock CMOS,” IEEE Transactions Circuits and Systems, vol. 46, no. 7, pp. 857-861, July 1999.
[8] R. I. Bahar and F. Somenzi, “Boolean techniques for low power driven re-synthesis,” International Conference on Computer-Aided Design, pp. 428-432, 1995.
[9] A. Morgenshtein, A. Fish, and I. A. Wagner, “Gate-Diffusion Input (GDI) – A Power Efficient Method for Digital Combinatorial Circuits,” IEEE Transactions on VLSI Systems, vol. 10, no. 5, pp. 566-581, Oct. 2002.
[10] S. Posluszny et al., “Design methodology for a 1.0 GHz microprocessor,” Proc. IEEE International Conference on Computer Design, pp. 17–23, 1998.
[11] C. M. Lin, “A 4µm NMOS NAND structure PLA,” IEEE Journal of Solid-State Circuits, vol. 16, no. 2, Apr. 1981.
[12] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI design. Reading, MA: Addison-Wesley, pp. 304-307, 1998.
[13] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, Apr. 1992.
[14] A. P. Chandrakasan and R. W. Brodersen, “Minimizing power consumption in digital CMOS circuits,” Proc. IEEE, vol. 83, no. 4, pp. 498-523, Apr. 1995.
[15] W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, “Pass-transistor logic design,” Int. J. Electron, vol. 70, no. 4, pp. 739-749, 1991.
[16] I. S. Abu-Khater, A. Bellaouar, and M. I. Elmastry, “Circuit techniques for CMOS low-power high-performance multipliers,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 1535-1546, Oct. 1996.
[17] K. Yano, Y. Sasaki, K. Rikino, and K. Seki, “Top-down pass-transistor logic design,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 792-803, June 1996.
[18] T. Sakurai, “Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs,” IEEE Transactions Electron Devices, vol. 40, no. 1, pp. 118-124, Jan. 1993.
[19] V. Adler and E. G. Friedman, “Delay and power expressions for a CMOS inverter driving a resistive-capacitive load,” Analog Integrated Circuits Signal Processing, vol. 14, pp. 29-39, 1997.
[20] R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Hingham, MA: Kluwer Academic, 1985.