臺灣博碩士論文加值系統

本論文分析一個零相移脈寬調變混疊失真抑制的D類放大器並對其作最佳化與驗證。在系統最佳化的部分，針對最佳化品質因數的部分，實現了切換頻率、功率輸出級大小以及運算放大器的增益、頻寬與電流消耗之最佳化。實現的零相移PWM混疊失真抑制技術利用兩個前饋路徑來解決先前技術相位偏移的問題並且克服頻帶外衰減能力與頻帶內增益的權衡。因此，在消除脈寬調變混疊失真時不會犧牲對頻帶內失真的抑制能力且實現之技術根據功率輸出級失真的考量可以達到最佳的切換頻率。與現存之脈寬調變混疊失真抑制之技術相比，實現之技術可在最佳的切換頻率達到好的總諧波失真加雜訊，因此能夠完成一個最佳的靜態電流設計。
此晶片實現於TSMC 0.5微米技術，經驗證後，在8歐姆之負載下，此技術改善總諧波失真加雜訊量為15dB，跟現有文獻相比，此晶片實現達到在P/N輸出級下有-98.01dB總諧波失真加雜訊量，並具有最佳之靜態電流517微安培與最高的品質因數1416，在N/N輸出級下有-97.29dB總諧波失真加雜訊量，並具有最佳之靜態電流337微安培與最高的品質因數2010。

In this thesis, an analysis for class-D amplifier with zero-phase-shift PWM-Aliasing-Distortion reduction technique is optimized and verified. System optimization about switching frequency, power-stage sizing and OPAMP’s gain, bandwidth, current consumption for optimized figure-of-merit is realized. The realized zero-phase-shift PWM-Aliasing-Distortion reduction technique utilizes two feedforward paths to solve phase-shift problem in previous work and overcome the trade-off between out-of-band loop attenuation and in-band loop gain. Therefore, the PWM-Aliasing-Distortion reduced without sacrificing high in-band distortion suppression capability and the realized technique can achieve at the optimized switching frequency with power-stage distortion consideration. Compared with existing PWM-Aliasing-Distortion reduction techniques, the realized technique achieves a good total harmonic distortion plus noise (THD+N) performance with the optimized switching frequency, resulting in the optimized quiescent current design.
Implemented in TSMC 0.5μm technology, the realized technique verified to improve the lowest THD+N by around 15dB with an 8-Ω load. Compared with state-of-the-arts, this work achieves -98.01dB THD+N (A-weighting) with the optimized quiescent current of 517μA and the highest figure-of-merit of 1416 for P/N power stage and -97.29dB THD+N (A-weighting) with the optimized quiescent current of 337μA and the highest figure-of-merit of 2010 for N/N power stage .

摘要 I
Abstract II
Acknowledgments III
Table of Contents IV
List of Tables VI
List of Figures VII
CHAPTER 1. Introduction 1
1.1 Motivation 1
1.2 Organization 4
CHAPTER 2. Fundamentals of Class-D Audio Amplifiers 5
2.1 Power Loss Analysis 5
2.2 Open-loop Distortion Analysis 6
2.3 Closed-loop Distortion Analysis 8
2.4 Prior arts of PWM-Aliasing-Distortion Reduction 10
CHAPTER 3. System Design 16
3.1 Realized Zero-Phase-Shift PADR 16
3.2 Minimum Switching Frequency (fsw) Analysis 20
3.3 Loop Filter Design for Minimum fsw 24
3.4 Noise Analysis for Realized Zero-Phase-Shift PADR 25
3.5 OPAMP Requirement Analysis 28
3.6 Mismatch Analysis for Realized Zero-Phase-Shift PADR 33
3.6.1 Gain Mismatch 33
3.6.2 Differential-Path Mismatch 34
3.6.3 Delay Mismatch 35
3.7 Power Stage Sizing for Better Figure-of-Merit (FOM) 35
CHAPTER 4. Circuit Implementations 38
4.1 The Realized Architecture of Zero-Phase-Shift PADR 38
4.2 OPAMP in the Loop Filter 39
4.3 PADR Path and Zero-Phase-Shift Path 42
4.4 Comparator 43
4.5 Triangular Wave Generator 46
4.6 Power Stage 48
CHAPTER 5. Layout and Measurement Setup 52
5.1 Floorplan and Layout 52
5.2 Simulation Results 55
5.3 Measurement Setup 59
5.4 PCB Design Consideration 62
5.5 Comparisons 67
5.6 Measurement Results 68
CHAPTER 6. Conclusions and Future Works 71
6.1 Conclusions 71
6.2 Future Works 72
CHAPTER 7. Reference 73

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