臺灣博碩士論文加值系統

本論文提出一種具有疊接式架構的差動輸出參考電壓電路。本電路是利用BJT所具有的的正/負溫度係數特性參數互相補償，以實現一個具有零溫度係數的參考電壓電路。電路利用兩種架構去模擬驗證，並比較兩種電路架構之優缺點；相較於已知電路，本論文提出的電路具有架構簡單、較少晶片面積、不須使用運算放大器等優點。
本論文除了詳細敘述工作原理以外，並使用HSPICE及LAKER電路模擬軟體以0.35微米製程進行佈局前和佈局後模擬，電路供應電壓範圍分別是3.3V與5V，溫度變化範圍則為-20°C-120°C。根據模擬結果，雙疊接式電路架構可以有效提升電路的PSRR值；當供應電壓是3.3V，溫度為25°C時，使用一般疊接式電路架構，輸出電壓約為426.2mv，輸出電壓變化量為1.37mv，消耗功率為0.5149mW，PSRR約為-27.52dB。當供應電壓是5V，溫度為25°C時，而使用雙疊接式電路架構輸出電壓約500.27mv，輸出電壓變化量為1.0236mv，消耗功率為0.96502mW，PSRR約為-45dB；本論文電路模擬結果與理論推導相符合，可證明電路的可行性。論文提出之差動式參考電壓電路可適用於汽車電子裝置，以及各種數位和類比電路之中。

In this thesis, a differential-mode reference voltage circuit with cascode architecture has been proposed. The design principle is using both the positive and the negative temperature coefficient parameters in BJT to compensate each other, and then a zero temperature coefficient output reference voltage can be achieved. Circuit simulations has used two different circuit architectures to realize the reference voltage, and both the advantages and disadvantages have been discussed. As compared with the existed differential mode reference voltage circuits, the proposed circuits benefits from simpler circuit architecture, less chip area, and also they don''t need any operational amplifier .
Detailed design principle has been disclosed in this thesis, also the HSPICE and LAKER simulation programs with 0.35-μm process parameters have been used to perform the pre-layout and post-layout simulation. The supply voltages of the proposed circuits are 3.3V and 5V, respectively. The test temperature ranges from -20°C to 120°C. According to the simulation results, the double-cascode architecture can enhance the PSRR. When the supply voltage is 3.3V and the temperature is 25°C, the output voltage of the proposed cascode architecture reference voltage circuit is 426.2mv, the maximum output voltage variation is 1.37mv, the power dissipation is 0.5149mW, and the corresponding PSRR is -27.52dB. As the supply voltage is 5V and the temperature is 25°C, the output voltage of the proposed double-cascode architecture reference voltage circuit is 500.27mv, the maximum output voltage variation is only 1.0236mv, the power dissipation is 0.96502mW, and the corresponding PSRR is -45dB. All the simulation results are consistent with the theoretic analysis. The proposed circuits can be applied to vehicle electronic devices design and other digital and analog circuits.

目錄
摘要.................................... i
Abstract................................ii
誌謝.....................................iv
目錄.....................................v
符號說明..................................xii
第一章 緒論...............................1
1.1研究背景與動機..........................1
1.2設計流程...............................2
1.3研究重點...............................4
1.4論文架構...............................4
第二章 參考電壓原理 .........................5
2.1參考電壓介紹與原理.......................5
2.2電流源分析..............................6
2.3參考電壓電路架構.........................8
2.3.1二極體穩壓電路.........................8
2.3.2 MOSFET參考電壓電路...................10
2.3.3 BJT參考電壓電路......................12
2.4 PTAT 電流電路 .........................18
第三章 改良式CMOS參考電壓電路.................22
3.1改良式CMOS單端輸出參考電壓/電流電路.........22
3.1.1 單端輸出參考電壓電路工作原理.............23
3.1.2 單端輸出參考電流電路架構與設計...........24
3.2 差動模式CMOS參考電壓電路.................26
3.2.1 電路工作原理 .........................26
3.3 改良式差動模式CMOS參考電壓電路............28
3.3.1 改良式差動輸出參考電壓電路之一...........28
3.3.2 改良式差動輸出參考電壓電路之二...........31
第四章 模擬與量測結果........................36
4.1設計流程................................36
4.2電路模擬結果.............................38
4.2.1 單端輸出參考電壓電路....................38
4.2.2 差動模式輸出參考電壓電路.................45
4.2.3 改良式差動輸出參考電壓電路...............52
4.2.4 改良式疊接差動輸出參考電壓電路............60
4.3 電路晶片實現與晶片量測結果.................68
4.3.1 單端輸出參考電壓電路....................69
4.3.2 差動模式輸出參考電壓電路.................73
4.3.3 改良式差動模式輸出參考電壓電路............77
4.3.3 改良式疊接差動輸出參考電壓電路............81
第五章 結論.................................85
參考文獻....................................86
Extended Abstract.........................89
簡歷(CV)...................................92

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