臺灣博碩士論文加值系統

本論文為一個省面積且基於延遲鎖相迴路之除小數頻率合成器並利用在週期內重複使用延遲單元之方式實現。現今常用的中央處理器和圖形處理器皆採用多個頻率合成器分別給不同核心單元獨立使用，針對不同核心的工作狀態，動態地調整時脈頻率來提供不同的輸出頻率，同時隨著製程的演進，單位面積的製程成本持續成長，因此頻率合成器的面積必須小型化，並且維持同樣的效能。
傳統常見的頻率合成器像是鎖相迴路，一般由相位比較器、電流幫浦、濾波器、振盪器、除頻器所構成。另一種實現方式是倍頻式延遲鎖相迴路，在倍頻的觀念上和鎖相迴路是大同小異的，但其有的特點是用每週期的參考時脈訊號重載於延遲線中去運作，相比鎖相迴路，參考時脈訊號就能夠直接的壓制頻率振盪器的雜訊，結果就會有較佳相位雜訊的表現。而有鑑於傳統的倍頻式延遲鎖相迴路往往需要很大的面積來實現高倍率的輸出頻率，所以在這裡我們提出了在週期內重複使用延遲單元之實現方式，以有效達到減少面積及高倍率輸出頻率的效果，同時也作到除小數的功能，使輸出頻率能有更高解析度的應用。
本晶片使用台積電90奈米互補式金氧半製程，主動區域面積約0.068mm2，在供應電源1.2V下，參考頻率為10MHz，輸出0.6GHz-0.8GHz的頻率範圍，參考突波達到-34dBc，從10kHz積分至10MHz的有效抖動值為7.319ps，在偏移輸出頻率1MHz的相位雜訊為-109.81dBc/Hz，消耗20.4mW功率。

An area efficient DLL-based fractional-N frequency synthesizer with cyclic reuse of a delay cell scheme is designed and implemented in the thesis. Nowadays, CPUs and GPUs adopt a number of frequency synthesizers for individual core in order to provide different frequencies by dynamically adjusting the operation frequency. Along with the progress in process, the cost per unit area keeps increasing. For that reason, the area of frequency synthesizer needs to be shrunk with the same performance.
There are two kinds of circuits in the conventional frequency synthesizers in general. One is the Phase-Locked Loop (PLL), composed of Phase Detector (PD), Charge Pump (CP), Loop Filter (LP), Voltage-Controlled Oscillator (VCO), Divider (DIV) generally. The other circuit to be realized is the Multiply Delay-Locked Loop (MDLL). Much as the concept of frequency multiplication is almost the same between PLL and MDLL, the characteristic in MDLL is that the reference clock in every cycle can be reloaded to operate in the delay line. The reference clock can suppress the noise from VCO to obtain the better performance of phase noise. The conventional MDLL also occupies lots of areas to achieve higher multiple ratio; as a result, we propose the cyclic reuse of a delay cell scheme. It not only shrinks the area to acquire higher multiple ratio but also achieves the function of fractional-N to make use of higher resolution’s application.
This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.068mm2 and 0.6GHz - 0.8GHz operation frequency. The reference spur is -34 dBc and the phase noise is -109.81 dBc/Hz at 1MHz offset from carrier frequency. The power dissipation under 1.2V supplying is 20.4mW.

口試委員會審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
CONTENTS v
LIST OF FIGURES vii
LIST OF TABLES x
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization 3
Chapter 2 PLL and MDLL 4
2.1 Basic Concept of PLL 4
2.2 Building Blocks of PLL 5
2.2.1 Phase/Frequency Detector and Charge Pump 5
2.2.2 Loop Filter. 8
2.2.3 Voltage-Controlled Oscillator 9
2.2.4 Frequency Divider 11
2.3 The Linear Model for PLL 12
2.3.1 Linear Model of PFD and Charge Pump 13
2.3.2 Linear Model of Loop Filter 13
2.3.3 Linear Model of VCO 15
2.3.4 Linear Model of Frequency Divider 15
2.3.5 Stability Analysis of Phase-Locked Loop 16
2.4 General Design Procedures of Phase-Locked Loop 20
2.5 The Concept of Multiply Delay-Locked Loop 21
2.5.1 Delay-Locked Loop 21
2.5.2 The Linear Model for DLL 22
2.5.3 DLL-Based Frequency Synthesizer 24
Chapter 3 A DLL-Based Fractional-N Frequency Synthesizer with Cyclic Reuse of a Delay Cell Scheme 25
3.1 Introduction 25
3.2 Architecture 25
3.3 Implementation 28
3.3.1 Clock Separator 28
3.3.2 Phase Selector and Controller 30
3.3.3 Delay Line 35
3.3.4 Phase Detector 40
3.3.5 Digital Loop Filter 41
3.3.6 Edge Combiner 48
3.4 Simulation Results 49
Chapter 4 Experimental Results 53
4.1 Experimental Setup 53
4.2 Measurement Enviroment 54
4.3 Measurement Results 56
Chapter 5 Conclusion and Future Works 59
5.1 Conclusion 59
5.2 Future Works 59
REFERENCE 60

[1]Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, and Charlie Chung-Ping Chen, “A 6.7MHz-to-1.24GHz 0.0318mm2 Fast-Locking All-Digital DLL in 90nm CMOS.” IEEE Int. Solid-State Circuits Conference, Pages: 244-P.245, 2012.
[2]Behzad Razavi, “Relation Between Delay Line Phase Noise and Oscillator Phase Noise.” IEEE Journal of Solid-State Circuits, 2014.
[3]P. Park, J. Park, and S.-H. Cho, “An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS.” IEEE Int. Solid-State Circuits Conference, 2012.
[4]T.-K. Jang, X. Nan, “A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter.” IEEE Int. Solid-State Circuits Conference, 2013.
[5]Wei Deng, “A 0.048mm2 3mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique,” IEEE Int. Solid-State Circuits Conference Dig. Tech. papers, Feb. 2015.
[6]Werner Grollitsch and Roberto Nonis, “A Fractional-N, All-digital Injection-Locked PLL with Wide Tuning Range Digitally Controlled Ring Oscillator and Bang-Bang Phase Detection for Temperature Tracking in 40nm CMOS,” ESSCIRC, 12-15 Sept. 2016.
[7]Visvesh S. Sathe, Srikanth Arekapudi, Alexander Ishii, Charles Ouyang, Marios C. Papaefthymiou, and Samuel Naffziger, “Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor,” IEEE J. Solid-State Circuits, vol. 48, Pages: 140-149, January 2013.
[8]Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, “A 1.7GHz MDLL-Based Fractional-N Frequency Synthesizer with 1.4ps RMS Integrated Jitter and 3mW Power Using a 1b TDC,” IEEE Int. Solid-State Circuits Conference, 9-13 Feb. 2014.
[9]Geum-Young Tak, Kwyro Lee, “A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis,” IEEE Int. Solid-State Circuits Conference, 2 Feb. 2018.
[10]M. Gholami, M. Sharifkhani, M. Hashemi, “Covering VHF frequency band with novel DLL-based frequency synthesizer,” International Conference on Communications and Signal Processing, Pages: 297 – 299. 2011.
[11]M. Gholami, M. Gholamidoon, M. Hashemi, “New method to synthesize the frequency bands with DLL-based frequency synthesizer,” International Conference on Communications and Signal Processing, Pages: 300 – 304. 2011.
[12]Seungjin Kim, In-Young Lee, Sang-Sung Lee, Min Su Kil, Jeongki Choi, Jinho Ko, Sang-Gug Lee, “A UHF-band RFID Transmitter with Spur Reduction Technique using a DLL-based Spread-Spectrum Clock Generator,” IEEE Radio Frequency Integrated Circuits Symposium, Pages: 393 – 396, 2014.
[13]Behzad Razavi, Design of Analog CMOS Integrated Circuits, Boston: McGraw- Hill, 2001.
[14]Behzad Razavi, RF Microelectronics, Second Edition, Upper Saddle River, NJ: Prentice-Hall, 2012.
[15]Behzad Razavi, Design of Integrated Circuit for Optical Communications, New York: McGraw-Hill, 2002.
[16]Jri Lee, Communication Integrated Circuits, Jri Lee’s Website, 2018.
[17]劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006.