臺灣博碩士論文加值系統

本論文主要是在研究目前半導體製程中在矽晶圓上所引發的缺陷問題，而所引發的矽晶圓上的缺陷會降低製程上的良率。目前在半導體蝕刻上所遭遇到的問題多半是晶圓於蝕刻過程中所掉落的粉塵顆粒導致晶圓缺陷的產生。在蝕刻過程中會因為粒子掉落於矽晶圓表面上並且在電漿蝕刻下而形成晶圓上的缺陷；而此次實驗的主要目的是改變乾式電漿蝕刻的方式，利用此蝕刻的方法，可以讓蝕刻中的粒子不容易掉落於晶圓表面上而形成缺陷，此方法能大幅度降低半導體晶圓表面的缺陷問題，進而能有效提高晶圓製程的良率。

The induced defects of Si wafer are common phenomena in semiconductor process for IC fabrications. The reduction of defects in each semiconductor process is the most important task to achieve high yield in manufacture of ICs. Dropping particles during semiconductor process are common to generate the induced defects, especially during dry etch process when the process chamber is filled with ionized plasma. The purpose of this thesis is to investigate the dropping -particle-induced defects by plasma dry etch process. The data resulted from both types of process are presented and compared in detail in relation to the process parameters of both processes. I conclude that, by proper tuning of dry etch parameters, the plasma dry etch process is superior to alleviate the problem of dropping-particle induced defects.

摘　　要 iii
ABSTRACT iv
誌　　謝 v
目　　錄 vi
表　　目　　錄 viii
圖　　目　　錄 ix
第一章 緒論 1
1.1 半導體簡介 1
1.1.1 半導體應用 2
1.1.2 矽晶圓面積的比較 4
1.1.3 乾式蝕刻的流程 5
1.2 蝕刻過程中所造成的缺陷問題 7
1.2.1 半導體的缺陷分佈 8
1.3 缺陷所導致的良率降低問題 10
第二章 理論推導 11
2.1 乾式電漿蝕刻原理 11
2.2 電漿蝕刻過程 18
2.3 此次實驗的蝕刻理論 19
第三章 實驗架構 21
3.1 實驗設計 21
3.2 蝕刻速率下降的問題 24
3.3 實驗製備 26
3.3.1 實驗蝕刻速率的比較 26
3.3.2 設計不同的實驗組 28
3.3.3 實驗組的電子束分析結果 30
第四章 實驗結果 34
4.1 實驗的偵測數據結果 34
4.1.1 蝕刻速率的比較 34
4.1.2 粉塵顆粒的結果 38
4.1.3 故障偵測的分析結果 43
4.2 本次實驗的各項數據結果 46
4.2.1 CDSEM結果的比較 46
4.2.2 實驗的厚度結果 51
4.2.3 電子束分析結果及粗糙度 54
4.2.4 實驗的結構剖面結果 57
4.2.5 實驗的缺陷分析結果 59
4.3 實驗的電性測試與良率結果比較 62
4.3.1 電性測試分析結果 62
4.3.2 電性曲線分佈趨勢比較 63
4.3.3 整體電性結果分佈比較 64
4.3.4 可靠性評估的測試結果 67
4.3.5 良率結果的比較 68
4.3.6 良率分佈圖的對照結果 70
第五章 結論 74
參　　考　　文　　獻 76

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