臺灣博碩士論文加值系統

鎖相迴路設計中針對不同產品有不同產品規格，因而把全部規格做到最好是
沒有意義的，同時只會浪費硬體成本而已，本論文重點是視產品規格需求，而特
別去修改某一部分電路特性，已達到成本和規格互相平衡情況。
於是開始設計如何使用最少硬體成本，在不會改變原來電路特性的情況下，
來減少鎖相電路的鎖定時間，使鎖相迴路的鎖定速度加快。另外系統轉移函數中，
壓控振盪器在系統是一個高通函數，所以壓控振盪器的雜訊會完全貢獻在輸出頻
率上，所以必需利用電路的技巧及修改壓控振盪器架構來減少相位雜訊，進一步
設計出具低劇跳特點的鎖相迴路。本研究也分別對各項產品規格，頻寬設計和穩
定度做一個介紹及探討。
本研究提出之鎖相迴路系統是具有電壓調節機制功能，在鎖相迴路設計中，
將加入電源重置開啟電路及電壓調節電路來改善鎖相迴路特性。典型在設計鎖相
迴路系統時，系統迴路頻寬如果設計比較小時，劇跳會變小，穩定速度也相對變
慢，鎖定時間和相位雜訊之間是交互限制作用的關係。當系統電源開啟時，穩定
速度往往會不如我們預期結果。系統中如要改善穩定速度這項規格時，可以利用
電源開啟瞬間，提前到達預估的振盪頻率，如此一來，就可以大幅改善因為低迴
路頻寬的設計所產生漫長系統時間。接下來只剩下相位比較的問題，而相位比較
時也可利用同步技術來加速系統的穩定速度。如此可以保有原來的相位雜訊及提
高系統中的穩定速度。
本論文所提出之想法，國內外並沒有相關資料記載，相信此想法對鎖相迴路
的設計有一定的幫助。本論文所提出之想法初期定義在消費性產品的應用，例如:
PDA/微處理器 中睡眠模式之喚醒系統及應用在頻率改變之系統均能有效率加速
系統快速穩定。

Every product has different specification, so it is meaningless to design all
specification to the best and produce high cost. This paper is to modify some circuit
based on product specification in order to make balance of cost and specification.
We start to study how to use the least cost to reduce Locking time and increase
locking speed of phase lock loops without modifiying original circuit characteristics. In
addition, VCO circuit in the system is a high pass filter. Noise of VCO will make
contribution to output frequency. So, we must use technique of designing circuit and
modify VCO structure to decrease phase noise and design a phase lock loops with
low-jitter characteristic further. Therefore, this study will introduce and discuss each
product specification, bandwidth design and stability.
The paper use the function of Voltage Regulator Circuit to improve the
characteristic of Phase Lock Loops by adding power on reset circuit and Voltage
Regulator circuit. In fact, if Band Width of Low Pass Filter in Phase Lock Loops system
is designed small, jitter will decrease while setting speed will increase. In other words,
the relationship of locking time and phase noise is trade-off. When power is on, the
result of setting speed don’t always achieve our expectation. Therefore, we can try to
advance the initial value of predicted oscillator’s frequency in the transient stage of
power on. This approach will save the time of which the system compares frequency.
For the part of phase detector, it can stable time speedily by adopting synchronism
concept to speed up the setting speed in system. By doing so, the initial phase noise can
be kept and setting speed in system can be increased.
This is a new idea without relative international papers and I believe this design
will make contribution to the design of Phase Lock Loops. Intial ideas will make
application in consuming products, such as wake-up system of sleep mode in
PDA/micro-control, and apply to make fast stability in changing frequency.

目 次
摘要................................ iv
英文摘要............................ v
致謝................................ vi
目次................................ vii
表目錄.............................. x
圖目錄.............................. xi
第一章 緒論......................... 1
1.1 研究動機........................ 1
1.2 研究目標........................ 1
第二章 鎖相迴路電路分析及架構....... 2
2.1 電壓控制振盪器.................. 2
2.1.1 環型振盪器.................... 4
2.1.2 三級環型振盪器................ 5
2.1.3 電壓控制振盪器.................10
2.2 簡單鎖相迴路.................... 10
2.2.1 相位檢測器.....................11
2.2.2 基本鎖相迴路技術...............13
2.2.3 鎖相迴路波形鎖定狀態...........14
2.2.4 在鎖定狀態之小瞬變現象.........17
2.2.5 簡單鎖相迴路之動態現象.........19
2.3 電荷幫浦鎖相迴路................ 23
2.3.1 鎖定獲得的問題.................23
viii
2.3.2 相位／頻率檢測器和電荷幫浦.....24
2.3.3 基本電荷幫浦鎖相迴路...........27
2.3.4 相位頻率檢測器／電荷幫浦鎖相迴路非理想特性........33
2.3.5 鎖相迴路之劇跳.................37
第三章 突破電路改良與設計........... 40
3.1 系統規格........................ 40
3.2 系統構架........................ 44
3.3 系統狀態模擬.................... 45
3.4 電壓控制振盪器之電路............ 50
3.5 低相位雜訊電壓控制振盪器之電路改善.... 53
3.6 低通濾波器之電路................ 58
3.7 相位頻率檢測器之電路............ 61
3.8 可規化分壓器/電壓調節之電路..... 61
3.9 鎖相迴路模擬.................... 65
3.10 電壓控制振盪器之改善........... 66
3.11 系統架構改良................... 69
3.12 加入電源重置之電路............. 71
3.13 電壓調節之電路................. 73
3.14 電荷分配問題................... 77
3.15 鎖相迴路之電路改良式........... 78
第四章 鎖相迴路佈局與量測........... 80
4.1 佈局............................ 80
4.2 量測............................ 81
第五章 總結及未來工作............... 84
5.1 總結............................ 84
ix
5.2 未來工作........................ 84
參考文獻............................ 85
符號彙編............................ 87
作者簡介............................ 88
x

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