臺灣博碩士論文加值系統

與傳統積體電路設計的流程做對照，如何做內部訊號的分配在晶片堆疊式系統級封裝中扮演了很重要的部分。本論文使用簡化連線模式去定義在晶片堆疊式系統級封裝設計中打線接合的結構，並且在任兩條內部訊號之間，給定一個可容忍的距離，做為之後做交叉限制的判斷，再利用產生動態的軌線去表示在堆疊上每一個連接接合端點可能的連線路徑，之後再以產生的動態軌線為基礎提出了一個動態左邊緣的分配方法。動態左邊緣的方法是以反覆執行的方式從第一層往下做訊號分配，並且必須滿足統一限制、幾何限制和交叉限制三種連接上的限制。
由實驗中跑測試例子的結果可以得知，使用簡化連線模式去表示打線接合的方法比沒有使用簡化連線模式的方法，可以分配更多的訊號而且連線的總長度也明顯的降低許多。

Compared with the traditional flow in IC designs, the assignment of inter-die signals is an important stage in a die-stacking SiP design. Given a tolerant distance between two different inter-die signals, the crossing constraint between two different inter-die signals can be defined, and a connection graph for all the pads in any boundary stack can be constructed by using a simplified wiring mode for the bonding wires in a die-stacking SiP design. Furthermore, a set of dynamic tracks can be defined from the corresponding connection graph. Based on the definition of the dynamic tracks in a connection graph, a dynamic left-edge approach is proposed to iteratively assign all the inter-die signals onto feasible pads under the three connection constraints：the unique, geometric and crossing constraints.
Compared with the heuristic approach without using simplified wiring mode, the experimental results show that our proposed approach can assign more inter-die signals and reduce the total wirelength for the tested examples.

摘 要............................................. i
Abstract......................................... ii
致謝.............................................. iii
表目錄............................................. vi
圖目錄............................................. vii
第一章 簡介....................................... 1
1.1 積體電路的發展............................... 1
1.2系統設計技術的發展............................. 2
1.3 常見的系統級封裝類型.......................... 6
1.3.1 晶片模組(Multi-chip Module)......... 6
1.3.2 多晶片封裝(Multi-chip Package)....... 7
1.3.3晶片堆疊(Die stacking)................ 7
1.3.4 封裝上的封裝方式(Package on Package).. 8
1.3.5 封裝內的封裝方式(Package in Package).. 9
1.4 系統級封裝中的互連技術......................... 9
1.4.1 打線接合(Wire bonding).............. 9
1.4.2覆晶接合(Flip chip bonding).......... 10
1.4.3矽穿孔(Trough Silicon Vias, TSVs).... 10
1.5 在晶片堆疊式系統級封裝的連接方式................. 11
1.5.1 輸入/輸出的接合端點................... 11
1.5.2 訊號連接的幾何限制(Geometric constraint) 12
第二章 相關研究與研究動機............................ 14
2.1相關研究..................................... 14
2.2 研究動機.................................... 17
第三章 簡化連線模式與問題描述 .................. 18
3.1 簡化連線模式(Simplified Wiring Model)........ 19
3.2 連線間可能有相交時的判斷....................... 22
3.2.1座標系的直線參數式...................... 23
3.2.2 旋轉座標軸........................... 24
3.3 內部訊號線之間的交叉限制(Crossing Constraint).. 26
3.4 問題描述.................................... 28
第四章 在晶片堆疊式SiP設計上具有簡化連線模式之有效訊號連接設定 30
4.1修改型左邊緣方法(Modified left-edge approach)... 32
4.1.1 定義Z-區段(Z-intervals).............. 33
4.1.2 將Z-區段分割到四個邊................... 34
4.1.3 定義動態的軌線........................ 36
4.1.3.1 動態軌線的選擇...................... 37
4.1.4 反覆的訊號分配........................ 38
4.1.4.1 分配Z-區段......................... 38
4.1.4.2 重新產生動態的軌線................... 39
第五章 實驗結果..................................... 42
第六章 結論與未來展望................................ 46
參考文獻........................................... 47

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