臺灣博碩士論文加值系統

　　本篇論文是以視訊應用規格為主，設計出低功率、解析度十二位元、操作時脈每秒兩百五十萬次取樣速率數位類比轉換器。在編碼方面，由於考量到電路的線性度表現，還有晶片面積的大小，所以採用低位元及高位元不同的編碼；低位元採用二進位權重，高位元採用溫度計編碼。除此之外，為了增進數位類比轉換器的動態效能，使用了抑制突波的拴鎖器，同時也考量了在佈局繞線時產生的寄生電容，所造成速度還有信號不同步的效應。
　　這個數位類比轉換器採用0.25 mm 1P5M mixed-signal CMOS製程來實現，整體晶片的核心面積為0.43 mm2，加入PADs之後為1.67 mm2。當設定條件為每秒250百萬次取樣速率，模擬結果表現出即使在接近二分之ㄧ取樣速率時，位元有效數也可高達十一位元。

　　The goal of this research was to design a low power 12-bit, 250 MHz digital-to-analog converter suitable for applications in video. The proposed DAC composed of segmented coding method for MSB and LSB bits, where the thermometer way for MSB and binary-weighted for LSB. Besides, to promote linearity of performance and suppress undesired glitch, the signal controlled differential switches of current sources is pre-processed by de-glitch latch. There is trade-off between accuracy and area for mismatch issue of current sources. The routing complexity and parasitic capacitance have to be taken into account for speed and signal synchronization.
　　This DAC is to be implemented in a 0.25 mm 1P5M mixed-signal CMOS process provided by TSMC, with active area of 0.43 mm2 (760 mm × 560 mm) and total area including PADs is 1.67 mm2 (1291 mm × 1291 mm). The simulation results revealed ENOB of 11.24 bit at Nyquist rate transition for 250 MSPS.

Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 1

Chapter 2. Digital-to-Analog Converter Architecture 5
2.1 Operations of DAC 5
2.2 Digital coding 6
2.3 Fundamentals of DAC’s parameters 6
2.3.1 Static parameters 7
2.3.2 Dynamic parameters 9
2.3.3 Spectrum parameters 12
2.4 Charge scale architecture 16
2.5 Voltage scale architecture 17
2.6 Current scale architecture 19
2.7 Segmented architecture 22

Chapter 3. Circuit Design Techniques of DAC 25
3.1 Overview 25
3.2 Digital phase 25
3.2.1 Thermometer decoders 25
3.2.2 Switching scheme 28
3.2.3 Input registers 30
3.2.4 Switch drivers 31
3.3 Analog phase 35
3.3.1 Random errors of current sources 35
3.3.2 Finite output impedance of current source 42
3.3.3 Bias circuits 44
3.3.4 Clock generator 48
3.4 Layout implementation 51

Chapter 4. Simulation Results and Testing Setup 53
4.1 Simulation results 53
4.1.1 Preparation for whole chip simulations 53
4.1.2 Input pattern generation 53
4.1.3 Output result analysis 54
4.2 Evaluation board design 61
4.2.1 Grounding 61
4.2.2 Bypassing and decoupling 61
4.2.3 Digital input 61
4.2.4 Output configuration 62

Chapter 5. Conclusions and Future Work 64
5.1 Conclusions 64
5.2 Future work 64

References 66

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