臺灣博碩士論文加值系統

本篇論文提出一顆具有可調變式快速傅立葉轉換處理器的晶片。這個系統主要包含三個主要的部份，分別是可調變式快速傅立葉轉換(Reconfigurable Fast Fourier transform)處理器、梅爾倒頻譜參數(Mel Frequency Cepstrum Coefficient)擷取晶片以及算數邏輯運算單元(ALU)架構的數位信號處理器。我們採用了可調變架構來設計快速傅立葉轉換處理器。同時為了降低晶片的功率消耗、計算量以及使電路更具彈性，在這篇論文我們採用一種新的暫存器陣列方法並使用radix-22演算法架構，此快速傅立葉轉換處理器可應用於語音信號辨識、影像處理和通訊系統之使用。梅爾倒頻譜參數晶片應用TSMC 0.13um 標準單元(standard cell)合成出處理器電路，Gate count約為4767，而latency 時間約為2.60μs，工作頻率為100MHz。

This thesis proposed the chip design of speech recognition for multimedia system. It is composed by three cores: a reconfigurable fast Fourier transform (FFT) processor, a Mel-scale frequency cepstrum coefficient (MFCC) circuit, and a dual-ALU digital signal process (DSP) processor with dynamic time warping speech recognition algorithm. In this FFT processor, we used the reconfigurable architecture to design our FFT processor. We proposed a novel register array based pipelined radix-22 structure to reduce power consumption and computation cycles. The FFT processor can be widely used in speech recognition, image process and communication system. The MFCC chips are synthesized by TSMC 0.13um cell library. The gate count of the MFCC chip is about 4767. The latency is about 2.60μs. The MFCC chip is work at 100 MHz.

1. Introduction 1
1.1 Preview of the FFT/IFFT processor 2
1.2 Preview of the MFCC chip 4
1.3 Preview of the DSP processor 5
1.4 Preview of our proposed dual-ALU DSP processor 6
2. Overview of the System 14
2.1 Introduction 14
2.2 DTW algorithm 15
3. The Chip Design of Reconfigurable FFT Processor 19
3.1 Introduction 19
3.2 FFT Algorithm 21
3.3 Hardware Architecture of the Reconfigurable FFT Processor 25
3.4 Hardware Architecture of Butterfly Unit 27
3.5 Hardware Architecture of Register Array 29
3.6 Hardware Architecture of Address Generator 30
3.7 Hardware Architecture of Control Unit 35
3.8 Summary of Reconfigurable FFT Processor 36
4. The Chip design of Mel Frequency Cepstrum Coefficient 37
4.1 Introduction 37
4.2 Hardware Architecture of Mel Filter Banks 40
4.3 Hardware Architecture of Logarithm Unit 41
4.4 Hardware Architecture of DCT Unit 44
4.5 Summary of MFCC Circuit 45
5. Implementation and Simulation Results 48
5.1 Cell-Based IC Design Flow 48
5.2 Implementation Results for Reconfigurable FFT Processor 51
5.3 Implementation Results for MFCC Chip 53
6. Conclusion 58

Bibliography 59

[1]M. Hasan, T. Arslan, and J. S. Thompson, “A delay spread based low power reconfigurable FFT processor architecture for wireless receiver,” IEEE International Symposium on System-on-Chip, 2003, pp. 135-138.
[2]Y. Zhao, A. T. Erdogan, and T. Arslan, “A low-power and domain-specific reconfigurable FFT fabric for system-on-chip applications,” IEEE International Symposium on Parallel and Distributed, 2005, pp. 169a-169a.
[3] G. Liu, and Q. Feng, “ASIC design of low-power reconfigurable FFT processor,” IEEE International Conference on ASIC, 2007, pp. 44-47.
[4] A. Ahmadinia, B. Ahmad, and T. Arslan, “System level modelling of reconfigurable FFT architecture for system-on-chip design,” Second NASA/ESA Conference on Adaptive Hardware and Systems, 2007, pp. 169-175.
[5] G. D. Wu, and Y. Lei, “A register array based low power FFT processor for speech recognition,” Journal of Information Science and Engineering, vol. 24, no. 3, 2008, pp. 981-991.
[6] M. C. Chang ,“VLSI design of register array based fast Fourier transform processor,” Master Thesis, National Chi Nan University, Taiwan, R.O.C., 2007.
[7] J. C. Wang, J. F. Wang, and Y. S. Weng, “Chip design of mel frequency cepstrum coefficient for Speech Recognition,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 6, 2000, pp. 3658-3661.
[8] B. D. Liu and H. H. Lin, “Implementation of MFCC processor design for speech feature extraction,” Master Thesis, National Cheng Kung University, Taiwan, R.O.C., 2001.

[9] H. Hassler, and N. Takagi, “Function evalution by table look-up and address,” Proceeding of the 12th Symposium on Computer Arithmeti, 1997, pp. 10-16 c.
[10] J. W. Cooley, and J. W. Tukey, “An algorithm for the machine calculation of complex Fourier series,” Math. Comp., vol. 19, 1965, pp.297-301.
[11] G. Bi, and E. V. Jones, “A pipelined FFT processor for word-sequential data, ” IEEE Trans. Acoust., Speech, Signal Processing, Dec. 1989.
[12] W. C. Yeh, and C. W. Jen, “High-speed and low-power split-radix FFT”, IEEE Trans. Acoustics, Speech, and Signal Processing, Vol 51, 2003, pp. 864 – 874.
[13] H. Sakoe, and S. Chiba, “Dynamic programming algorithm optimization for spoken word recognition,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 26, 1978, pp. 43-49.
[14] H. F. Silverman, and D. P. Morgan, “The application of dynamic programming to connected speech recognition,” IEEE ASSP Magazine, vol. 7, 1990, pp. 6-25.
[15] L. Rabiner, A. Rosenberg, and S. Levinson, “Conderations in dynamic time warping algorithms for discrete word recognition” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 26, 1978, pp. 575-582.
[16]M. B. Bevan, “A Low-Power, High-performance,1024-point FFT processor,” IEEE Journal of Solid-State Circuits, vol. 34, no. 3, 1999, pp. 380-387.
[17]L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, “Implementation of a low power 128-point FFT Processor,” in Proceedings of Fifth International conference on Solid-State and Integrated Circuit Technology, 1998, pp. 369-372.
[18]K. S. Stevens and B. W. Suter, “A mathematical approach to a low power FFT Architecture,” in Proc. IEEE International Symposium on Circuits and Systems, 1998, pp. II-21-II-24.
[19] Logic Synthesis with Design Compiler, Inc. January 2006.
[20] Y. Chen, Y. W. Lin, and C. Y. Lee, “A block scaling FFT/IFFT processor for WiMAX applications, ” in Proc. 2nd IEEE Asian Solid-State Circuits Conference, 2007, pp. 203–206.
[21] Y. W. Lin, H. Y. Liu, and C. Y. Lee, “A dynamic scaling FFT processor for DVB-T applications,” IEEE Journal of Solid-State Circuits, vol. 39, 2004, pp. 2005-2013.