臺灣博碩士論文加值系統

應用於H.264/AVC當中的全文自適應二進制算術編碼器是一種在碼率壓縮方面最先進的技術。然而，其產出率卻會受限於位元層級的資料相關性。此外，只有部分硬體化的CABAC編碼器無法支援即時處理超高解析度的視訊，例如：QFHD（3840 × 2160）。因此，在本篇論文中，我們提出了一個全硬體化的CABAC編碼器。根據對輸入資料所做的分析與統計，我們所提出的新架構包含了：一個可處理多位元的算數編碼器、一個可減少執行週期數的全文模型機制。為了能夠支援多位元算數編碼器，我們提出了一個新的記憶體存取方式。並且，考量到整體運行時，不同模組之間產出率的平衡，我們也設計了一個支援一次多個輸出入的緩衝器來使我們的算數編碼其與全文模型機制之間執行時，不會產生不必要的停滯。
我們的架構最多可一次處裡八個位元。當其執行時脈為222MHz時，在H.264/AVC所定義的最大碼率下，也能夠支援即時編碼QFHD視訊。此外，因為我們的架構能夠針對所有輸入資料當中最主要的部分做有效率的編碼，所以我們在更高品質的視訊下可以節省更多的執行週期數。我們已經將所提出的CABAC編碼器整合到一個H.264/AVC 編碼器的系統之中，並且運行在一個多媒體系統晶片的平台上。

Abstract I
Contents II
List of Figures IV
List of Tables VI
Chapter 1 Introduction 1
Chapter 2 CABAC Algorithm for H.264/AVC 3
2.1 Binarization Schemes 4
2.2 Context Modeler 7
2.3 Binary Arithmetic Encoding Algorithm 11
2.3.1 Regular Coding Engine 11
2.3.2 Bypass Coding Engine 13
2.3.3 Terminal Coding Engine 14
2.4 CABAC Encoding Flow 15
Chapter 3 Previous Works 20
3.1 Introduction of Our Previous Work 20
3.2 Related works 22
Chapter 4 Design Consideration and Analysis 25
4.1 Design Consideration 25
4.2 Bin Distribution Analysis 25
Chapter 5 Proposed Architecture 30
5.1 Overview of the Proposed Architecture 30
5.2 SE-Type-Specific Cycle-Reduction Schemes in BCM 32
5.2.1 Cycle-Reduction Scheme for Sig_coeff_flag, Last_sig_coeff_flag and Coeff_level Types 33
5.2.2 Cycle-Reduction Scheme for Cbf Type 35
5.3 Pipeline Organization of Our Multi-bin BAE Architecture 38
5.3.1 Design Strategy for Context Memory Access 40
5.3.2 Design Strategy for Interval Subdivision and Renormalization 44
Chapter 6 Experimental Result 53
6.1 Implementation Results 53
6.2 Comparison 57
Chapter 7 Conclusion 59

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