臺灣博碩士論文加值系統

隨著製程設計的進步，使得處理器越來越複雜，速度也越來越快，使得這些高速處理器的測試面臨到空前的挑戰，原本利用外部測試機的測試的方法也因成本過高及測試機固有的不精確性，而沒有辦法滿足全速測試，因此，軟體實作自我測試便成了極具吸引力的測試方法，因為這種方法採用處理器本身的指令傳送測試資炓，而且不需要修改處理器內部架構，也不需加入額外的硬體成本，再加上以軟體實作，使得這種方法更有彈性。
本篇論文為了達到高品質的固定缺陷蓋率而提出了一種軟體實作處理器自我測試的方法，先將處理器依據功能性分成數個不同性質的元件，以這些元件為主執行測試，以降低測試處理器時的複雜度；接著從處理器的指令集架構及暫存器轉換層級硬體描述檔案所獲得的資訊，依據不同功能性的元件將處理器指令分類，這些分類的指令限制了ATPG工具產生的測試圖樣，以排除無法執行的測試圖樣。當每個測試圖樣從主要輸入端輸入時，便會監視這個測試圖樣在每個不同元件的輸出輸入端所造成的變化，直到主要輸出端，並將會造成同樣變化的測試圖樣移除，最後剩下來的測試圖樣都能被對應到處理器的任一道指令，形成測試程式。
我們利用一顆簡單的處理器-PARWAN來證明這篇論文所提出的測試方法，實驗結果顯示所產生的4.5KB測試程式在7000個測試時間內，可以達到80%的缺陷涵蓋率。產生測試程式的方法並不是一個自動且系統化的方法，但是因為移除了重覆的測試圖樣，所以雖然測試程式的產生不有效率，但卻可以降低測試執行時間。

It is very hard to achieve at-speed testing of high-speed processors using external testers due to the technical and economical feasibility. Hence, software-based test is an attractive method due to using processors instructions and without requiring design changes and or insertion of any additional hardware structures.
This thesis presents a software-based test methodology for a processor core to achieve high fault coverage and small code size. In order to reduce the test complexity, the processor core is firstly partitioned into several components according to their functionality. The associated instructions for each component are identified via the ISA and RTL code of the processor core. These associated instructions are utilized as constraints for the ATPG tool to eliminate the instruction unimplemented test patterns. The data path transition during each test pattern applied from primary input to primary output will be exhaustively monitored and compared to remove the redundant test patterns among different components. Finally all test patterns will be mapped to instructions which are integrated as a test program.
A simple accumulator-based processor core, PARWAN, is used to demonstrate the feasibility of this methodology. The result shows that a test program with 4.5KB code size can achieve the 80% fault coverage within 7000 test cycle time. The whole test program generation is not yet an automatic and systematical processing. Because the exhaustive algorithm is used to compare and remove redundancy, the test generation is not time-efficient but the test application is expeditious.

目錄
誌謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 v
表目錄 vi
第一章 導論 1
第二章 背景知識 3
2-1 微處理器模型 4
2-2 硬體測試 7
2-2.1 DFT 7
2-2.2 Scan-based 8
2-2.3 BIST 內建式自我測試 11
2-3 軟體測試 14
2-3.1 功能性軟體測試 16
2-3.2 結構性軟體測試 17
2-3.3 高階層結構性軟體測試 21
第三章 軟體實作處理器的自我測試 24
3-1 架構相依性 25
3-2實作方法論 28
3-3評估效能 41
第四章 實驗結果 43
第五章 結論與未來展望 45
參考文獻 46

[1] K. Batcher and C. Papachristou, “Instruction Randomization Self Test For Processor Cores,” Proc. VLSI Test Symposium, pp. 34-40, San Diego, California, 1999.
[2] F. Corno, G. Cumani, M. S. Reorda and G. Squillero, “Fully Automatic Test Program Generation for Microprocessor Cores,” Design, Automation and Test in Europe Conference and Exhibition, pp.1006-1011, March 3-7, 2003, Munich, Germany.
[3] L. Chen and S. Dey, “Software-Based Self-Testing Methodology for Processor Cores,” IEEE Trans. Computer-Aided Design, vol.20, no.3, pp. 369-380, March 2001.
[4] L. Chen and S. Dey, “DEFUSE: A Deterministic Functional Self-Test Methodology for Processors,” Proceedings of the 18th IEEE VLSI Test Symposium, pp.255 - 262, April 2000, Montreal, Canada.
[5] L. Chen, S. Dey, P. Sanchez, K. Sekar and Y. Chen, “Embedded Hardware and Software Self-testing Methodology for Processor cores,” Design Automation Conference, pp. 625 - 630, June 2000, Los Angeles, CA.
[6] A. Giani, S. Sheng, M. S. Hsiao and V. D. Agrawal, “Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip environment,” 19th IEEE VLSI Test Symposium, pp. 163-168, March 29 - April 03, 2001, Marina Del Rey, CA.
[7] I. J. Huang, C. F. Kao, H. M. Chen, C. N. Juan and T. A. Lu, “A Retargetable Embedded In-Circuit Emulation Module for Microprocessors,” IEEE Design and Test, pp. 28-38, vol. 19, Issue: 4, July/August 2002.
[8] K. Jayaraman, V. M. Vedula and J. A. Abraham, “Native Mode Functional Self-Test Generation for Systems-on-Chip,” Proceedings of International Symposium on Quality Electronic Design, pp. 280- 285, 2002, San Jose, California.
[9] N. Kranitis, D. Gizopoulos, A. Paschalis and Y. Zorian, “Instruction-Based Self-testing of Processor Cores,” IEEE VLSI Test Symposium, pp. 223-228, April 28-May 1, 2002, Monterey, CA, USA.
[10] N. Kranitis, D. Gizopoulos and Y. Zorian, “Effective Software Self-Test Methodology for Processor Cores,” IEEE Design Automation and Test in Europe Conference, pp. 592-597, March 2002, Paris, France.
[11] N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis and Y. Zorian, “Low-cost Software-Based Self-Testing of RISC Processor Cores,” IEEE Design Automation and Test in Europe Conference, Munich, Germany, March 2003.
[12] N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos and Y. Zorian, “Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores,” International Test Conference, pp. 431-440, 09 30 - 10 02, 2003, Charlotte, NC, USA.
[13] A. Krstic, W. -C. Lai, L. Chen, K. -T. Cheng and S. Dey, “Embedded Software-Based Self-Testing for SoC Design,” Design Automation Conference, pp. 355-360, 2002, New Orleans, Louisiana, USA.
[14] A. Pashalis, D. Gizopoulos, N. Kranitis, M. Psarakis and Y. Zorian, “Deterministic Software-Based Self-Testing of Embedded Processor Cores,” Proceedings of the conference on Design, automation and test in Europe, pp 92-96, 2001, Munich, Germany.
[15] J. Shen and J. A. Abraham, “Native Mode Functional Test Generation for Processors with Applications to Self Test and Design Validation,” Proceedings. Intel. Test Conference, pp.990-999, October 1998, Washington DC.
[16] B. W. Johnson, “Design and Analysis of Fault Tolerant Digital Systems,” pp. 24-37, pp. 463, USA: Addison-Wesley Publishing Company, 1989.
[17] D. Y. Jung, S. H. Kwak and M. K. Lee, “Reusable Embedded Debugger for 32 bit RISC Processor Using the JTAG Boundary Scan Architecture,” Proceedings Of 2002 IEEE ASIA-PACIFIC Conference on AISC, vol.3, No. 1, pp. 209 – 212, 2002.
[18] 吳正一, “Structural-Fault Oriented Test Program Generation for Microprocessors,” 全國博碩士論文資訊網, 國家圖書館索書號:91NTU00428067.
[19] 孫清華, “JTAG 測試原理與應用,” p1-2~p2-12, 臺北市：全華科技圖書股份有限公司, 2000[民89]
[20] SoC測試技術探索
http://ieknet.itri.org.tw/commentary/example/1-3.pdf
[21] 數位邏輯電路之內建式自我測試
http://www.taiwansoc.org/download/member_file/2002/test/2002-12-1.pdf