臺灣博碩士論文加值系統

本論文仔細探討了CMOS元件中熱載子的可靠性。首先，在淺溝槽隔離層元件中，提出了與元件寬度相關的熱載子衰退的結果與討論。對現今甚或未來使用淺溝槽隔離層的CMOS超大型積體電路來說，這是一個非常關鍵性的課題。其中，厚閘極氧化層與薄閘極氧化層元件卻存在著不同的淺溝槽隔離層效應。接著，我們將討論最先進的應變矽元件的介面可靠性，對這樣一個嶄新結構的元件來說，這樣的討論對其電性分析將是很重要的一環。
對於使用複式氧化層CMOS技術與淺溝槽隔離層結構的p型元件，提出了與元件寬度相關的熱載子衰退的結果。使用複式氧化層CMOS技術P型金氧半元件的各種特性與現象，將是我們第一次觀察到，對於ALD和Plasma結構的氧化層也做進一步的研究探討。實驗的結果顯示的現象，操作電流在熱載子加壓之後的衰退會隨著元件寬度的變小而更嚴重，對於厚氧化層(大於30 Å)元件來說，這操作電流的衰退是因為通道長度變小的效應，此時在氧化層缺陷中的電子是造成這現象的主因。但是對超薄氧化層元件(小於20 Å)而言，操作電流的衰退卻是起因於通道寬度的變窄，而影響主因也變成了氧化層中的電洞。熱載子衰退隨著元件寬度的縮小，對厚氧化層p型元件會造成關閉狀態電流的增加，然而對薄氧化層元件而言，則是臨界電壓的變大。
本論文的第二部分，探討主題則是集中在先進應變矽元件的可靠性分析。為了要研究應變矽元件的介面可靠性。我們將使用新發展出來的差頻電荷幫浦量測法，從實驗數據分析，我們首次發現了兩階的電荷幫浦最大電流，這顯示了兩層的介面缺陷被我們的實驗所探測，包含氧化層/矽基板，與矽/矽化鍺這兩層介面。最後，論文中還利用此方法來對這個新世代元件，進行熱載子加壓之後的各種電性分析。

This thesis addresses the issues related to hot carrier reliabilities in CMOS devices. At first, results on the width dependent hot-carrier (HC) degradation for shallow-trench-isolated (STI) CMOS devices are presented. This is a very crucial issue for the present and future CMOS ULSI using STI technologies. Both thick gate oxide and thin gate oxide exhibit different effects for STI CMOS devices. And then, the analysis of interface reliability in the most advanced strained-silicon devices will be studied. It is important to evaluate the electric property of the new structure device.
For the study of STI induced reliability, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) p-MOSFET’s in a multiple oxide CMOS technology. For the first time, different phenomena in p-MOSFET’s for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide p-MOSFET’s. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick gate oxide (above 30Å), the ID degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for ultra-thin gate oxide (below 20Å), the ID degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced VT are significant. The degradation in thick-oxide p-MOSFET’s causes an increase of off-state leakage current and an increase of VT for that in thin-oxide with reduced width.
The final part of the thesis is focused on the reliability characterization of most advanced strained-silicon MOSFET's. In order to investigate the interface property of strained-silicon MOSFET's, an advanced charge-pumping measurement is performed. From the experimental data, we found a two-level maximum charge-pumping current for the first time. It reveals that two layers of interface, including gate oxide/silicon and silicon/silicon germanium, are detected. Finally we apply hot carrier stress to evaluate the electrical reliability of this new generation devices.

Contents
Acknowledgements v
Chinese Abstract vi
English Abstract viii
Contents x
Figure Captions xiii
Chapter 1 Introduction 1
1.1 The Motivation of This Work 1
1.2 Organization of This Thesis 3
Chapter 2 Experimental Measurement Setup and Basic Theory 5
2.1 Introduction 5
2.2 Experimental Setup 5
2.3 Gated Diode Measurement 7
2.3.1 Experimental Setup 7
2.3.2 Basic Theory 7
2.4 Charge Pumping Measurement 9
2.4.1 Experimental Setup 9
2.4.2 Basic Theory 11
2.5 Summary 12
Chapter 3 Enhanced Width Dependent Hot-Carrier Effect in Shallow-Trench-Isolation p-MOSFET’s 13
3.1 Introduction 13
3.2 Device Fabrication 14
3.3 Results and Discussion 16
3.3.1 Observations of the Width-Dependent Effect in p-MOSFET’s 16
3.3.2 Physical Model for the Narrow Width Enhanced Degradation in STI Edge p-MOSFET’s 16
3.4 Summary 24
Chapter 4 The Impact of NBTI on Scaled STI Narrow Width p- MOSFET’s with Advanced ALD N/O Gate Stack in the Direct Tunneling Regime 26
4.1 Introduction 26
4.2 Device Preparation 26
4.3 Results and Discussion 27
4.3.1 Narrow Width Effect at Room Temperature 27
4.3.2 Observation of Narrow Width Dependent NBTI Effect 35
4.3.3 Further Insight of the Trap Generation and the Model 35
4.4 Summary 40
Chapter 5 Analysis of Hot Carrier Degradation in Strained Silicon MOSFET’s with Charge Pumping Method 45
5.1 Introduction 45
5.2 Device Preparation 45
5.3 Results and Discussion 46
5.3.1 Analysis with the Improved Charge Pumping Method 46
5.3.2 Hot Carrier Degradation in Strained-Si Devices 52
5.3.2.1 Analysis of HC Degradation with Impact Ionization Substrate Current 52
5.3.2.2 Analysis of HC Degradation with Channel Carrier Mobility 56
5.3.2.3 Analysis with Ge Concentration and Thickness of Si layer 60
5.3.2.4 Analysis of Temperature Dependent HC Degradation 63
5.4 Summary 69
Chapter 6 Summary and Conclusion 71
References 72

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