臺灣博碩士論文加值系統

本篇論文由兩個部分組成，包含了低雜訊放大器，以及具傳輸零點濾波器之5/60GHz 雙模態接收機。
第二章會先對低雜訊放大器的設計做探討，利用0.18μm SiGe製程實現一個5.8GHz電感耦合低雜訊放大器，及利用0.15μm PHEMT製程比較不同自偏壓架構的低雜訊放大器對溫度效應的影響。
第三章會說明5/60 GHz雙模態接收機的電路設計。此接收機使用TSMC 0.18-μm CMOS製程，為了能有效的改善頻帶外訊號干擾，在5 GHz訊號路徑中加入具傳輸零點主動射頻通道選擇濾波器。並利用蕭基二極體（ft接近200 GHz）設計被動混頻器來處理60 GHz訊號，以解決電晶體ft在0.18-μm製程中過低的問題。

This thesis consists of two parts, including a low noise amplifier and a 5/60 GHz dual-mode receiver with transmission zeros filter.
In chapter 2, we describe the low noise amplifier. And then, we use trifilar-type component implementing low noise amplifier in 0.18μm SiGe technology. Otherwise, we use 0.15μm PHEMT technology to discuss temperature effects in two different self-bias architectures of low noise amplifier.
Chapter 3 introduces the circuits in 5/60 GHz dual-mode receiver will be illustrated. It is implemented in 0.18-μm CMOS technology. In order to improve the signal interference, we use an active RF filter with transmission zeros on 5GHz path. Furthermore, A passive mixer is designed for 60 GHz signal to solve the insufficient ft problem in 0.18-μm technology by using schottky diode of which the ft is nearly 200 GHz.

中文摘要.....................................................................................................................i
英文摘要 ii
誌謝...................................................................................................................iii
目錄 iv
圖目錄 vi
表目錄 viii
第 1 章 導論 1
1-1 研究動機 2
1-2 論文組織架構 3
第 2 章 射頻前端電路 4
2-1 前言 5
2-2 低雜訊放大器設計分析 6
2-2-1 使用源極退化電感之疊接式低雜訊放大器 7
2-2-2 分析如何達到輸入阻抗與雜訊之匹配 8
2-3 實作1:5.8GHz 低雜訊放大器(SiGe 0.18um) 10
2-3-1 研究動機 10
2-3-3 晶片模擬及量測結果 14
2-3-4 結果與討論 16
2-4 實作2:2.4GHz 低雜訊放大器(PHEMT 0.15μm) 18
2-4-1 研究動機 18
2-4-2 電路架構 18
2-4-3 電路分析 19
2-4-4 電路設計 21
2-4-5 模擬結果 23
2-4-6 結果與討論 27
第 3 章 5/60GHz 雙模態接收機 28
3-1 前言 29
3-2 接收機架構 29
3-3 變壓器回授之低雜訊放大器 30
3-4 具傳輸零點之主動帶通濾波器設計分析 32
3-5 使用蕭基二極體之次諧波混頻器設計 39
3-6 可切換式主動混頻器 42
3-7 實作1:5GHz 具傳輸零點主動濾波器 43
3-8 實作2:具傳輸零點主動濾波器之5/60GHz雙模態 47
第 4 章 結論 54
參考文獻 56

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