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[1] K. Kim, C.-G. Hwang, and J.-G. Lee,“DRAM Technology Perspective for Gigabit Era,”IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 598-608, Mar. 1998. [2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Second Edition, Cambridge University Press, 2009. [3] H. Sunami, T. Kure, N. Hashimoto, K. Toyabe, and S. Asai, “A Corrugated Capacitor Cell (CCC),” IEEE Trans. Electron Devices, vol. ED-31, no. 6, pp. 746-753, Jun. 1984. [4] L. Nesbit, J. Alsmeier, B. Chen, J. Debrosse, P. Fahey, M. Gall, J. Gambino, S. Gernhardt, H. Ishiuchi, R. Kleinhenz, J. Mandelman, T. Mii, M. Morikado, A. Nitayama, S. Parke, H. Wong, and G. Bronner, “A 0.6μm2 256Mb Trench DRAM Cell with Self-Aligned BuriED Strap (BEST),” in IEDM Tech. Dig., Dec. 5-8, 1993, pp. 627-630. [5] D. Temmler, “Multilayer Vertical Stacked Capacitors (MVSTC) for 64Mbit and 256Mbit DRAMs,” in VLSI Symp. Tech. Dig., May 28-30, 1991, pp. 13-14. [6] T. Kaga, T. Kure, H. Shinriki, Y. Kawamoto, F. Murai, T. Nishida, Y. Nakagome, D. Hisamoto, T. Kisu, E. Takeda, and K. Itoh, “Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAMs,”IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 255-261, Feb. 1991. [7] H. Shinriki, Y. Nishioka, Y. Ohji, and K. Mukai, “Oxidized Ta2O5/Si3N4 Dielectric Films on Poly-Crystalline Si for Dram’s,” IEEE Trans. Electron Devices, vol. 36, NO. 2, pp. 328-332, Feb. 1989. [8] S. W. Yang, W. S. Liao, L. Economikos, A. Guliani, D. Yang, B. Y. Kim, D. Dobuzinsky, and S. Shih, “Structural Demonstration of Cost Effective Isolation Trench Fill for Sub-110nm Vertical Trench DRAM and SOC Applications,” in Int. Symp. VLSI Tech. Sys. Appl., Oct. 6-8, 2003, pp. 117-120. [9] W. Mueller, G. Aichmayr, W. Bergner, M. Goldbach, T. Hecht, S. Kudelka, F. Lau, J. Nuetzel, A. Orth, T. Schloesser, A. Scholz, A. Sieck, A. Spitzer, M. Strasser, P. F. Wand, S. Wege, and R. Weis, “Trench DRAM Technology for the 50nm Node and Beyond,” in Int. Symp. VLSI Tech. Sys. Appl., Apr. 24-26, 2006, pp. 1-2. [10] H.-J. Wann and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate,” in IEDM Tech. Dig., 1933, pp. 635-638. [11] S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A SOI Capacitor-less 1T-DRAM Concept,” in Proc. IEEE Int. SOI Conf., Oct. 2001 , pp. 153-154. [12] P. Fazan, S. Okhonin, M. Nagoga, J. M. Sallese, L. Portmann, R. Ferrant, M. Kayal, M. Pastre, M. Blagojevic, A. Borschberg, and M. Declercq, “Capacitor-less 1T-transistor DRAM ” in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 10-13. [13] P. C. Fazan, S. Okhonin, M. Nagoga, and J.-M. Sallese, “A Simple 1-Transistor Capacitor-less Memory Cell for High Performance Embedded DRAMs,” in Proc. IEEE Custom Integrated Circuit Conf., 2002, pp. 99-102. [14] D.-i. Bae, S. Kim, and Y.-K. Choi, “Low-cost and highly heat controllable capacitorless PiFET (Partially insulated FET) 1T DRAM for embedded memory,” IEEE Trans. on Nanotechnology, vol. 8, no. 1, pp. 100-105, Jan. 2009. [15] J.-W. Han, S.-W. Ryu, S. Kim, C.-J. Kim, J.-H. Ahn, S.-J. Choi, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “A Bulk FinFET unified-RAM (URAM) cell for multifunctioning NVM and capacitorless 1T-DRAM,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 632–634, Jun. 2008. [16] T. Tanaka, E. Yoshida, and T. Miyashita, “Scalability Study on A Capacitorless 1T-DRAM: from Single-gate PD-SOI to Double-gate FinDRAM, ” in IEDM Tech. Dig., 2004, pp. 919-922. [17] T. Shino, I. Higashi, K. Fujita, T. Ohsawa, Y. Minami, T. Yamada, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto, and A. Nitayama, “Highly Scalable FBC (floating body cell) with 25nm BOX Structure for Embedded DRAM Applications,” in VLSI Symp. Tech. Dig., Jun. 2004, pp. 132-133. [18] J.-T. Lin, K.-D. Huang, and B.-T. Jhrng, “Performance of a Capacitorless 1T-DRAM Using Polycrystalline Silicon Thin-Film Transistors with Trenched Body,” IEEE Electron Device Lett., vol. 29, no. 11, pp. 1222-1225, Nov. 2008. [19] K.-W. Song, H. Jeong, J.-W. Lee, S. I. Hong, N.-K. Tak, Y.-T. Kim, Y. L. Choi, H. S. Joo, S. H. Kim, H. J. Song, Y. C. Oh, W.-S. Kim, Y.-T. Lee, K. Oh, and C. Kim, “55nm Capacitor-less 1T DRAM Cell Transistor with Non-overlap Structure,”in IEDM Tech. Dig., 2008, pp. 1-4. [20] E. Yoshida, and T. Tanaka, “A Capacitorless 1T-DRAM Technology Using Gate-induced Drain-leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692-697, Apr. 2006. [21] J.-W. Han, S.-W. Ryu, S.-J. Choi, and Y.-K. Choi, “Gate-induced Drain-leakage (GIDL) Programming Method for Soft-programming-free Operation in Unified RAM (URAM),”IEEE Electron Device Lett., vol. 30, no. 2, pp.189-191, Feb. 2009. [22] S. Puget, G. Bossu, C. Fenouiller-Beranger, P. Perreau, P. Masson, P. Mazoyer, P. Lorenzini, J.-M. Portal, R. Bouchakour, and T. Skotnicki,“FDSOI Floating Body Cell eDRAM Using Gate-induced Drain-leakage (GIDL) Write Current for High Speed and Low Power Applications,” in Proc. IEEE Int. Memory workshop Conf., May 2009, pp. 1-2. [23] G. Kim, S.-W. Kim, J.-Y. Song, J.-P. Kim, K.-C.Ryoo, J.-H. Oh, J.-H. Park, and H.-W. Kim, B.-G. Park, “Body-raised Double-gate structure for 1T DRAM,” in Proc. IEEE Nano. Materials and Devices Conf., Jun. 2009, pp. 1-6. [24] N. Collaert, M. Aoulaiche, M. Rakowski, B. De Wachter, K. Bourdelle, B.-Y. Nguyen, F. Boedta, D. Delprat, and M. Jurczak, “Analysis of Sense Margin and Reliability of 1T-DRAM Fabricated on Thin-film UTBOX Substrates,” in Proc. IEEE Int. SOI Conf., Oct. 5-7 2009, pp. 1-2. [25] M. Bawedin, S. Cristoloveanu, and D. Flandre,“A Capacitorless 1T-DRAM on SOI based on Dynamic Coupling and Double-Gate Operation,”IEEE Electron Device Lett., vol. 29, no. 7, pp. 795-798, Jul. 2008. [26] Z. Zhou, J. G. Fossum, and Z. Lu, “Physical Insights on BJT-based 1T DRAM Cells,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 565-567, May 2009. [27] D.-I. Moon, S.-J. Choi, J.-W. Han, S. Kim, and Y.-K. Choi, “Fin-Width Dependence of BJT-Based 1T-DRAM Implemented on FinFET,” IEEE Trans. Electron Devices, vol. 31, no. 9, pp. 909-911, Sep. 2010. [28] M. Aoulaiche, N. Collaert, R. Degraeve, Z. Lu, B.D. Wachter, G. Groeseneken, M. Jurczak, and L. Altimime, “BJT-Mode Endurance on a 1T-RAM Bulk FinFET Device,” IEEE Trans. Electron Devices, vol. 31, no. 12, pp. 1380-1382, Dec. 2010. [29] N. Rodriguez, F. Gamiz, and S. Cristoloveamu,“ARAM Memory Cell Concept and Operation,”IEEE Electron Device Lett., vol. 31, no. 9, pp. 972-974, Sep. 2010. [30] N. Rodriguez, S. Cristoloveamu, and F. Gamiz,“Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible with Bulk and SOI Substrates”IEEE Electron Device Lett., vol. 58, no. 8, pp. 2371-2377, Aug. 2011. [31] M. G. Ertosun, P. Kapur, and K. C. Saraswat, “ A Highly Scalable Capacitorless Double Gate Quantum Well Single Transistor DRAM:1T-QW DRAM,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1405-1407, Dec. 2008. [32] H. Jeong, K.-W. Song, I. H. Park, T.-H. Kim, Y. S. Lee, S.-G. Kim, J. Seo, K. Cho, K. Lee, H. Shin, J. D. Lee, and B.-G. Park, “A New Capacitorless 1T DRAM Cell:Surrounding Gate MOSFET with Vertical Channel (SGVC Cell),” IEEE Trans. on Nanotechnology, vol. 6, no. 3, pp. 352-357, May 2007. [33] M. G. Ertosun, H. Cho, P. Kapur, and K. C. Saraswat, “A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM, ” IEEE Electron Device Lett., vol. 29, no. 6, pp. 615-617, May 2008. [34] J. S. Shin, H. Bae, J. Jang, D. Yun, J. Lee, E. Hong, D. H. Kim, and D. M. Kim, “A Novel Double HBT-Based Capacitorless 1T DRAM Cell with Si/SiGe Heterojunctions, ” IEEE Electron Device Lett., vol. 32, no. 7, pp. 850-852, Jul. 2011. [35] F. Gamiz, N. Rodriguez, and S. Cristoloveanu, “ 3D Trigate 1R-DRAM Memory Cell for 2x nm Node,” in IEEE Int. Memory Workshop Conf., May 2012, pp. 1-4. [36] U. Avci, I. Ban, D. Kenche, and P. Chang, “Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX,” in Proc. IEEE Int. SOI Conf., 2008, pp. 29–30. [37] R. Ranica, A. Villaret, P. Mazoyer, D. Lenoble, P. Candelier, F. Jacquet, P. Masson, R. Bouchakour, R. Foumel, J. P. Schoellkopf, and T. Skotnicki, “ A One Transistor Cell on Bulk Substrate (1T-Bulk) for Low-cost and High Density eDRAM,” in VLSI Symp. Tech. Dig., Jun. 2004, pp.128-129. [38] S. Okhonin, M. Nagoga, E. Carman, R. Begffa, E. Faraon,“New Generation of Z-RAM,”in IEDM Tech. Dig., Dec. 2007, pp. 925-928. [39] ISE TCAD 10.0, User’s Manual.
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