臺灣博碩士論文加值系統

WiMAX無線通信採用正交頻分多工(Orthogonal Frequency Division Multiplexing)調制技術以支持高速數據通訊能力。用戶端實際連線之速率與容量需求將透過WiMAX技術規範:靈活之頻寬範圍(1.25 MHz ~20 MHz)與可適應性之調變機制(BPSK, QPSK, 16QAM及64QAM)予以實現之。對於像WiMAX具備多重頻段與多重速率要求之無線通信系統，其射頻收發訊系統之設計挑戰相對提高；另一方面，更要求系統具備可適應性與可配置性之能力，以因應用戶端實際連線各種不同服務之需求。
隨著CMOS製程技術之日益進步，射頻訊號處理系統之設計趨勢在於儘早對類比射頻訊號數位化並進行數位訊號處理過程，藉此以消除對精密且昂貴類比電路之依賴需求。對於目前使用之寬帶離散時間三角積分調變器(Wide-band Discrete-Time Sigma-Delta Modulator)，當WiMAX系統訊號轉換頻寬增加時；更高速與更有效率之類比積分器規格將成為系統效能之最終瓶頸。
本論文將針對運用於WiMAX中頻收發訊系統之「時間交錯式四路徑帶通三角積分調變器」提出系統化之設計方法。有關調變器效能等特性，我們將使用Filter Solutions與SIMULINK行為模擬軟體進行分析與驗證作業；其中對存在於運算放大器之非理想特性，包括: Jitter衝擊，kT/C雜訊，有限直流增益，有限單位增益頻寬，迴轉率，DAC雜訊等；並與雜訊轉換函數(Noise Transfer Function, NTF)之極點/零點優化進行逐一驗證討論。更重要地，本論文提出了一套系統化極點/零點優化分析技巧，並可應用於「多重路徑時間交錯式帶通三角積分調變器」之設計應用。

WiMAX wireless communication uses Orthogonal Frequency Division Multiplexing (OFDM) to transfer high data rates. The standard offers flexible bandwidths between 1.25MHz to 20MHz and different modulation schemes including BPSK, QPSK, 16QAM and 64QAM to enable WiMAX systems to adaptively change the speed and capacity of the wireless connection based on the practical demand. For such a multi-band, multi-speed system imposes significant challenges in transceiver blocks and requires adaptability and re-configurability to cope with different requirements.
With the ongoing advance of the CMOS technology, the trend is that digitizing an analog signal and performing digital signal processing is as early as possible in a signal processing system, to eliminate the requirements of accurate and expensive traditional analog building blocks. As WiMAX desired signal conversion bandwidth increases, the higher speed and more efficient integrator circuits becomes the main bottleneck in the present wideband discrete-time Sigma-Delta modulators.
In this thesis, we would provide a systematic design method for four-path time-interleaved band-pass Sigma-Delta modulator for the IF transceiver of WiMAX application. The modulator performances would be analyzed and verified by Filter Solutions and SIMULINK behavioral simulations, also the most important non-ideal performance in the OP amplifier such as: jitter impact, kT/C noise, finite DC gain, finite GBW, slew rate, DAC noise and NTF pole/zero optimization has been verified. By the way, this systematic method could provide a new analysis skill of pole and zero optimization for multi-path time-interleaved Sigma-Delta modulator significantly.

Abstract (in Chinese)
Abstract (in English)
Acknowledgements (in English)
List of Figures
List of Tables

Chapter 1 Introduction
1.1 Motivation
1.2 Contributions
1.3 Thesis Organization

Chapter 2 WiMAX Overview
2.1 Introduction
2.2 WiMAX PHY Layer
2.2.1 OFDMA Fundamentals
2.2.2 OFDMA Symbol Structure and Sub-Channelization
2.3 WiMAX MAC Layer
2.3.1 Quality of Service (QoS) Support
2.3.2 MAC Scheduling Service
2.4 Considerations of WiMAX RF Architecture
2.4.1 Time Division Duplex (TDD) Architecture
2.4.2 Frequency Division Duplex (FDD) Architecture
2.4.3 Half Frequency Division Duplex (HFDD) Architecture
2.5 Summary

Chapter 3 Fundamentals of the Sigma-Delta Modulator
3.1 Introduction
3.2 Performance Metrics
3.2.1 Peak SNR/SNDR, DR and SFDR
3.2.2 Nyquist Rate
3.2.3 Oversampling Rate (OSR)
3.2.4 Power Dissipation
3.2.5 Figure of Merit (FOM)
3.3 Quantization Noise Analysis
3.3.1 Oversampling
3.3.2 First Order Noise Shaping
3.3.3 Second Order Noise Shaping
3.3.4 Generalization
3.4 Non-ideal Effects
3.5 Multi-Stage Noise Shaping
3.6 Modeling Analysis of Sigma-Delta Modulator
3.6.1 Clock Jitter
3.6.2 Thermal Noise
3.6.3 OP Amplifier Noise
3.6.4 Integrator Leakage
3.6.5 Integrator Weight Variation
3.6.6 OP Amplifier Finite BW and SR
3.6.7 Comparator Non-idealities
3.6.8 DAC Non-linearity
3.7 Topologies of Sigma-Delta Modulator
3.7.1 Single-Loop Sigma-Delta Modulator
3.7.1.1 Chain of Integrators with Distributed Feedback (CIFB)
3.7.1.2 Chain of Integrators with Weighted Feed-forward Summation (CIFF)
3.7.1.3 CIFB with Input-Signal Feed-forward (CIFB-IF)
3.7.1.4 CIFF with Input-Signal Feed-forward (CIFF-IF)
3.7.2 Time-Interleaved Sigma-Delta Modulator
3.7.3 Continuous-Time Sigma-Delta Modulator
3.8 Summary

Chapter 4 Pole and Zero Optimization of Time-Interleaved Sigma-Delta Modulator Design for the WiMAX Applications
4.1 Introduction
4.2 Architecture
4.2.1 Clock Jitter at the Input Sampler
4.2.2 Switch Thermal Noise (kT/C Noise) and OP Amplifier Thermal Noise
4.2.3 OP Amplifier’s Non-ideality
4.2.4 Multi-bit DAC Error
4.3 Pole and Zero Optimization
4.3.1 Single-Path Optimization
4.3.2 Time-Interleaved Optimization
4.3.3 Optimization Guidelines
4.3.4 Optimization by Filter Solutions
4.4 Simulation Results
4.4.1 Modulator Output Spectrum Simulation
4.4.2 Jitter Simulation
4.4.3 PSD versus OP DCG and GBW Simulation
4.4.4 PSD versus OP Amplifier SR and DC Gain Simulation
4.5 Summary

Chapter 5 Circuit Implementation
5.1 SIMULINK Models Overview
5.2 Circuit Implementation
5.2.1 4-Path Clock Distribution
5.2.2 SCF Circuit for H1 & H2 Block
5.2.3 SCF Circuit for 8-Levels Quantizer with Adder
5.2.4 SCF Circuit for 3-bits DAC
5.3 SWITCAP II Simulations
5.3.1 Single-Path 2nd Order Low-Pass Sigma-Delta Modulator with Ideal OP Model
5.3.2 Real OP Model with Finite DC Gain and Bandwidth
5.3.3 Simulation Results by Ideal OP Model
5.3.4 Simulation Results by Real OP Model
5.4 Summary

Chapter 6 Conclusion and Future Work
6.1 Conclusion
6.2 Key Research Contributions
6.3 Future Work

References

Appendix
1. Mobile WiMAX Features
2. WiMAX Scalable OFDMA, TDD Frame Structure and Other Advanced PHY Layer Features
3. SWITCAP II Netlist
4. Papers in Submission

[1] IEEE Std. 802.16-2004. IEEE Standard for Local and Metropolitan Area Networks, Part 16: Air interface for fixed broadband wireless access systems.
[2] IEEE Std. 802.16e-2005 and IEEE Std. 802.16-2004/Cor1-2005. IEEE Standard for Local and Metropolitan Area Networks, Part 16: Air interface for fixed broadband wireless access systems, Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1.
[3] H. Yagoobi, “Scalable OFDMA Physical Layer in IEEE 802.16 WirelessMAN,” Intel Technology Journal, Volume 8, Issue 3, Aug. 2004.
[4] “WiMAX Forum Network Architecture - Stage 2: Architecture Tenets, Reference Model and Reference Points-Part1,” WiMAX Forum, Mar. 2007.
[5] B. Bisla, R. Eline, L. M. Franca-Neto, “RF System and Circuit Challenges for WiMAX,” Intel Technology Journal, Volume 8, Issue 3, Aug. 2004.
[6] A. Rusu, A. Borodenkov, M. Ismail, H. Tenhunen, “Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers,” Royal Institute of Technology (KTH) Stockholm, June, 2004.
[7] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, and A. Baschirotto, “Behavioral Modeling of Switched-Capacitor Sigma–Delta Modulators,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 50, No.3, Mar. 2003.
[8] A. Gharbiya, T. C. Caldwell, and D. A. Johns, “High-Speed Oversampling Analog-To-Digital Converters,” International Journal of High Speed Electronics and Systems, 2005.
[9] G. Nair, J. Chou, T. Madejski, K. Perycz, D. Putzolu and J. Sydir, “IEEE 802.16 Medium Access Control and Service Provisioning,” Intel Technology Journal, Volume 8, Issue 3, Aug. 2004.
[10] Nuhertz Technologies, LLC “Filter Solutions”
http://www.filter-solutions.com
[11] R. Schreier, “Delta Sigma Tool Box”http://www.mathworks.com/matlabcentral/fileexchange
[12] G. Bernardinis, F. Borghetti, V. Ferragina, A. Fornasari, U. Gatti, P. Malcovati and F. Maloberti, “A Wide-Band 280-MHz Four-Path Time-Interleaved Band-pass Sigma–Delta Modulator,” IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 53, No. 7, Jul. 2006.
[13] V. Ferragina, A. Fornasari, U. Gatti, P. Malcovati, and F. Maloberti, “Gain and offset mismatch calibration in time-interleaved multipath A/D sigma–delta modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 51, No. 12, pp. 2365–2373, Dec. 2004.
[14] C. H. Kuo, T. C. Hsueh and S. I. Liu, “Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm,” Analog Integrated Circuits and Signal Processing, 33, 289-300, 2002
[15] D. Akselrod, S. Greenberg, and S. Hava, “Multi-bit ΔΣ CMOS DAC Employing Enhanced Noise-Shaped DEM Architecture,” Electronics, Circuits and Systems, ICECS 2004
[16] B. E. Boser, B. A. Wooley, “The Design of Sigma-Delta Modulation Analog-to- Digital Converters,” IEEE Journal of Solid-State Circuits, vol. 23, no.6, Dec. 1998.
[17] R. Schreier and B. C. Temes, Understanding Dalta-Sigma Data Converters, John Wiley & Sons, 2005.
[18] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design 2nd Edition, Oxford University Press, 2002.
[19] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, 1997.