臺灣博碩士論文加值系統

　　本論文提出寬操作範圍和低功率消耗的低頻數位控制振盪器應用於無線近身網路，此數位控制振盪器不僅提供較佳的解析度，且能夠產生低頻訊號，和其他一般的方法比較，也達到較低的功率消耗及電路複雜度。
　　本論文提出兩個不同的低頻數位控制振盪器架構； 第一種是以串接的架構去維持解析度及頻率操作範圍，在90nm的製程下，頻率範圍為9.9~823 MHz，解析度為6.42 ps，功率消耗在10 MHz時為0.114 mW。另一種架構則是使用串接結合內插式架構來產生低頻訊號，且可達到較低的功率消耗，在0.18µm的製程下，頻率範圍為7.9~121 MHz，解析度為10.54 ps，功率消耗在7.9 MHz時為0.054 mW。此外，由於電路可以standard cell來實現，使它有較佳的可攜性，能夠很容易的用於不同的製程，且非常適合用在生醫系統晶片的應用上。

　　In this thesis, a wide range and a low power digitally controlled oscillator with low output frequency for wireless body area network (WBAN) are presented. The proposed digitally controlled oscillator not only can provide high
resolution, but also can generate low frequency clock signal with low power consumption and low circuit complexity as compared with conventional approaches.
　　This thesis presents two different low-frequency digitally controlled oscillator architectures; the first proposed architecture employs a cascade-stage structure to achieve high resolution and wide range at the same time. Simulation results show that the operation frequency range is from 9.9MHz to 823MHz, and the power consumption can be improved to 0.114mW (@10MHz) with 6.42ps resolution in 90nm CMOS process technology. The second proposed architecture employs a cascade-stage structure with interpolator to generate low output frequency, and achieve low power consumption, Simulation results show that the operation frequency range is from 7.9MHz to 121MHz, and the power consumption can be improved to 0.054mW (@7.9MHz) with 10.54ps resolution in 0.18µm CMOS process technology. In addition, the proposed clock generator can be implemented with standard cells, making it easily portable to different processes and very suitable for biomedical System-On-Chip (SoC) applications.

摘要 i
英文摘要 ii
目　錄 iii
表目錄 v
圖目錄 vi
第一章　介紹 1
1.1　研究動機 1
1.2　論文組成 4
第二章　數位控制振盪器概要 6
2.1　時脈產生器之應用 6
2.2　數位控制振盪器之設計 6
2.2.1　汲取電流式架構 6
2.2.2　驅動能力調變式架構 7
2.2.3　延遲路徑選擇式架構 8
2.2.4　數位控制變容器架構 9
第三章　低輸出頻率寬操作範圍數位控制振盪器設計 12
3.1　數位控制振盪器架構 12
3.2　子電路架構 13
3.2.1　史密特觸發延遲元件架構 13
3.2.2　粗調及微調級電路架構 14
3.2.3　遲滯延遲元件 15
3.3　模擬結果 16
第四章　低輸出頻率低功率消耗數位控制振盪器設計 23
4.1　數位控制振盪器架構 23
4.2　子電路架構 24
4.2.1　粗調級電路架構 24
4.2.2　內插式架構 25
4.3　模擬結果 27
4.4　性能比較表 30
第五章　實作結果 32
5.1　設計流程 32
5.2　Post – layout模擬結果 33
5.3　量測考量 39
第六章　結論與未來展望 46
參考文獻 47

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