臺灣博碩士論文加值系統

半導體之構裝機台設備由於涉及複雜的機構作動，導致機台設備錯綜複雜很難用數學的公式來模式化其參數設定與機台績效之關係。因而機台參數設定往往需要做許多嘗試錯誤或實驗設計造成相當多的時間與原料的浪費。本研究嘗試以Neural Network來模式化(Model)機台的行為，希望經訓練(Training)後的類神經網路可以幫助我們計算出適當的機台參數設定，以達到所欲達到的機台表現。
本研究以銲線機為載具，用倒傳遞Neural Network來模式化機台參數設定的行為，以實際的數據訓練Neural Network並驗證。本研究結果顯示為可行，同時透過本研究也達到降低試作次數、新產品換線機台的設定時間、人力、物料以及時間上耗費。

Because of the great physical complexity of the precision equipment used in semiconductor manufacturing , it is very difficult to mathematically model the machine behaviors for equipment parameter setting. Trial - and - errors and/or several runs of DOE (Design of Experiment) are often needed in equipment parameter settings for new product production. This research attempts to use Neural Network to model the machine behaviors in order to provide an approach for machine parameter setting thus eliminating or reducing the wasted materials, time, and other resources while conducting the search for proper parameter setting given a set of target machine performance.
The research used a two-layer back propagation network to model wire bonder machines used in the packaging industry. Real data from two I.C. packaging plants are used. The result shows that the method is feasible. Benefits of the approach include: reducing trial experiments, in machine setup for new products, thus reducing waste of materials, labors and times, and finding a intelligent method for parameter setting.

致謝詞 2
摘要 3
Abstract 4
表目錄 8
圖目錄 9
第一章、緒 論 10
1.1 研究背景與動機 10
1.2 研究目的與問題敘述 11
1.3 研究貢獻與成果 11
1.4 相關研究 11
第二章、文獻探討 13
2.1 類神經網路概要(Foundations of Neural Networks) 13
2.1.1 Neural Network架構 13
2.2 Matlab類神經網路工具箱介紹 19
2.2.1 Perceptron Network 20
2.2.2 Adaptive Linear Filters 20
2.2.3 Back propagation 21
2.2.4 Radial Basis Networks 22
2.2.5 Self-organizing networks 22
2.3 類神經網路之相關應用 23
2.3.1 Data Fusion 23
2.3.2 Forcasting 24
2.3.3 Optimization 24
2.4 文獻探討結語 25
第三章、研究載具介紹：半導體構裝封裝製程 26
3.1 半導體構裝產品簡介 26
3.1.1 DIP 26
3.1.2 SOP 27
3.1.3 LCC 27
3.1.4 PGA 27
3.1.5 QFP 28
3.1.6 BGA 28
3.1.7 覆晶接合技術 (Flip Chip) 29
3.1.8 多晶片模組 (MCMs, Multi Chip Module) 29
3.1.9 近似晶片尺寸封裝 (CSP, Chip Scale Package) 29
3.2 半導體構裝製程簡介 31
3.2.1晶圓背磨(Wafer Back Grinding) 32
3.2.2 晶圓切割(Die Saw) 32
3.2.3 黏晶(Die Attach) 32
3.2.4 銲線(Wire Bond) 33
3.2.5 封膠(Mold) 34
3.2.6 剪切/成型(Trim/Form) 35
3.2.7 蓋印(Mark) 35
3.3 銲線機構與製程簡介 35
3.3.1銲線機之銲線機構簡介 36
3.3.2銲線流程說明如下: 36
3.4 影響銲線成敗要素說明與銲線製程參數簡介 39
3.4.1材料因素 39
3.4.2銲線機的銲針(Capillary) 40
3.4.3導線架的影響 40
3.4.4製程參數的影響 40
3.5銲線績效指標 43
第四章、研究方法 45
4.1研究概念 45
4.2研究載具 47
4.3Neural Network Training樣本假設及預定抽樣計畫 47
4.3.1 Neural Network Training Sample預定抽樣計畫 47
4.3.2 Neural Network Training資料驗證與分析 47
4.4研究流程 48
4.4.1 參考文獻探討 48
4.4.2 訪談問卷設計 48
4.4.3 實地訪談與資料收集 48
4.4.4 問卷填寫與資料驗證 48
4.4.5 結果驗證與分析 49
4.4.6 設備選用管理模型修正 49
第五章實例應用 51
5.1 實驗環境設定 51
5-2機台參數設定實例應用 52
5.2.1 CASE 1：ASM AB309 Direct Model 52
5.2.2 CASE 2 : ASM AB309 Indirect Model 56
5.2.3 CASE 3：TOSOK UBD2100 Direct Model 59
5.2.4 CASE 4 : TOSOK UBD2100 Indirect Model 63
5.2.5實例應用結論 65
第六章結論與建議 67
6.1 結論 67
6.2 後續研究 68
參考文獻 70
附 錄 72
Program List(for ASM Direct Model) 72
Program List(for ASM Indirect Model) 74
Program List(for TOSOK Direct Model) 76
Program List(for TOSOK Indirect Model) 78
問卷表格 80

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