臺灣博碩士論文加值系統

電流式數位類比轉換器可以推動額外的負載並且使用於高速應用。近年來，許多數位類比轉換器實現於先進製程，特別是130奈米、90奈米製程。然而，就成本的考量而言，晶片面積越小越好。本論文將實現低成本高速高解析數位類比轉換器，並提出新的動態元件匹配演算法，該演算法可以抵抗電流源的不匹配誤差。並驗正動態元件匹配效應及改善電流緣不匹配所造成的非線性效應。為了得到較小的面積，本論文採用輸出阻抗校正機制以及動態元件匹配演算法，尤其是先進製程的應用。然而，本論文也採用歸零機制搭配輸出阻抗校正機制以改善高頻輸入訊號時的效能。
此外，我們也以90nm製程實現了一個12位元數位類比轉換器，可在1.2V電壓下達到1.4V差動輸出擺幅的數位類比轉換器，且得到較小核心面積。整體電路操做頻率為100MS/s。在低頻時，SFDR改善後為76.18dB；在高頻時則改善為70.19dB。其核心面積為0.06mm2。

Current-steering DAC can drive external loads, and usually used in high speed application. In recent years, many digital-to-analog converters have been implemented in advanced process, especially in 130nm, 90nm, and CMOS process. However, as far as the cost is concerned, the area of chip is getting as smaller as possible. In this thesis, a low-cost high resolution and high speed DAC is implemented. A new Dynamic Element Matching (DEM) algorithm is proposed. This algorithm can resist the mismatch error of current source. The effect of Dynamic Element Matching is verified and improves the non-linear effect caused by mismatch of current source. DEM algorithm and Output Impedance Calibration (OIC) are taken to get a smaller area of DAC, especially in advance process. However, the performance at high input frequency can be improved by OIC and return-to-zero.
Besides, a 12-bit DAC is physically implemented in 90nm CMOS process. It has ultra-wide output swing of 1.4-Vpp under 1.2V supply voltage and small area for active area. The SFDR of DAC using proposed DEM and OIC achieves 76.18dB in low input frequency and 70.19dB at Nyquist bandwidth with operating frequency of 100MS/s. The active area is 0.06mm2.

Table of Contents
Abstract (Chinese) I
Abstract (English) II
Acknowledgment III
Table of Contents IV
List of Tables VI
List of Figures VII

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization 2
Chapter 2 Fundamental of Nyquist-Rate DAC 4
2.1 Ideal DAC 5
2.2 Static Performances 6
2.3 Dynamic Performances 9
2.4 Zero-Order Hold Response 13
2.5 Architecture of Digital-to-Analog Converters 16
2.5.1 Resistor-String Based DAC 16
2.5.2 Binary-Weighted Resistor DAC 19
2.5.3 Charge-Redistribution DAC 22
2.6 Current-Steering DAC 23
2.6.1 Fundamental of Current-Steering DAC 24
2.6.2 Mismatch of Current Source 28
2.6.3 Finite Output Impedance Effect 31
2.6.4 Layout Technique 33
Chapter 3 New Dynamic Element Matching Algorithm 36
3.1 Conventional Data Weighted Averaging 37
3.2 Random Multiple Data Weighted Averaging 39
3.3 Proposed Dynamic Element Matching Algorithm 42
3.4 Output Impedance Calibration 47
3.4.1 Output Impedance Requirement 48
3.4.2 Input Code Pre-Distortion Technique 51
Chapter 4 Circuit Design and Physical Implementation 53
4.1 DAC Architecture 53
4.2 DEM Decoder 54
4.2.1 4-bit decoder 54
4.2.2 Linear Feedback Shift Register (LFSR) 55
4.2.3 Switch Controller 57
4.2.4 Shift Circuit 59
4.3 Switch Driver 60
4.4 Current Cell Architecture. 61
4.5 Return-to-Zero Circuit 62
4.6 Floorplan and Layout 63
Chapter 5 Simulation and Measurement Results 68
5.1 Simulation Results 68
5.2 Measurement Setup 73
5.2.1 Power Supply and Ground 73
5.2.2 Digital Input and Clock Termination 74
5.2.3 DAC Output Terminal 75
5.2.4 Measurement Environment Setup 75
5.3 Comparison 76
Chapter 6 Conclusions and Future Work 78
6.1 Conclusions 78
6.2 Future Work 79
References 80

List of Tables
Table 2-1 Summaries of binary-weighted, unary and segmented DACs 27
Table 2-2 Percentage of σ(I) to meet different DAC accuracy as
99.7% INL yield 30
Table 3-1 The switching operation between MSDEM and RMDWA 46
Table 3-2 Summary of the output impedance requirements for DNL and INL within 0.5 LSB 49
Table 3-3 Summary of the output impedance requirements for good SFDR 50
Table 4-1 Truth table of 4-bit decoder
55
Table 5-1 Performance Summary 72

Table 5-2 Comparison of FOM1 between published IEEE paper and this work 77

List of Figures

Figure 2-1 Digital-to-Analog interface 4
Figure 2-2 Block diagram of an N-bit DAC 5
Figure 2-3 Characteristic curve of an ideal 3-bit DAC 6
Figure 2-4 The illustration of DNL and INL for a N-bit DAC 7
Figure 2-5 The illustration of gain error and offset error 8
Figure 2-6 The illustration of monotonic and non-monotonic DAC 9
Figure 2-7 DAC output response of code transition 10
Figure 2-8 Illustration of glitch 11
Figure 2-9 Transfer curve of an ideal converter and its quantization noise 12
Figure 2-10 Probability density function for the quantization error, VQ 12
Figure 2-11 DAC system and signal reconstruction 14
Figure 2-12 Signal in time domain and frequency domain
(a) Discrete-time signal, xd(t), and its spectrum (b) Zero-order hold signal, xsh(t),and its spectrum (c) Signal after low-pass filter, xlp(t), and its spectrum 15
Figure 2-13 3-bit resistor-string DAC 17
Figure 2-14 3-bit resistor-string DAC with digital decoder 18
Figure 2-15 A 4-bit folded resistor-string DAC 19
Figure 2-16 4-bit binary-weighted resistor DAC 20
Figure 2-17 4-bit reduced-resistance-ratio DAC 20
Figure 2-18 R-2R resistance ladder 21
Figure 2-19 4-bit R-2R based DAC 22
Figure 2-20 4-bit R-2R DAC with equal currents through the switches 22
Figure 2-21 4-bit charge-distribution DAC 23
Figure 2-22 An N-bit binary-weighted current-steering DAC diagram 24
Figure 2-23 An N-bit unary DAC 25
Figure 2-24 An N-bit segmented DAC with M-bit LSB 26
Figure 2-25 Normalized required area versus percentage of segmentation 28
Figure 2-26 Random mismatches due to microscopic variations in device
dimensions 29
Figure 2-27 INL yield versus σ(I) for 8-bit, 10-bit, 12-bit and 14-bit DAC 30
Figure 2-28 Area vs. accuracy for 90nm process 31
Figure 2-29 Conventional current cell architecture with cascode transistor 32
Figure 2-30 Bode plot of output impedance with cascode configuration 32
Figure 2-31 ADC-DSP-DAC loop of calibration scheme 34
Figure 2-32 Illustration of dummy current cells 34
Figure 2-33 Q2 switching scheme(a) Q2 classical switching scheme (b) Q2
random walk switching scheme 34
Figure 2-34 Three different splitting implementation of current source (a) Unary current source implemented as one unit (b) Unary current source implemented as 4 units in parallel (c) Unary current source implemented as 16 units in parallel 35
Figure 3-1 Block diagram of multi-bit DAC 37
Figure 3-2 Conventional DWA operation 38
Figure 3-3 Operation of RMDWA with 2-pointers 39
Figure 3-4 Frequency spectra of DEM 40
Figure 3-5 Mismatch effect and DEM effect 41
Figure 3-6 Charge injection effect 42
Figure 3-7 The operation of MSDEM 43
Figure 3-8 Comparison of (a) Before DEM (b) After DEM 44
Figure 3-9 Comparison of (a) MSDEM (b) MSDEM+RMDWA 45
Figure 3-10 Comparison of MSDEM and proposed DEM 46
Figure 3-11 Proposed DEM algorithm 47
Figure 3-12 DNL and INL of differential-end DACs with different
resolution (a) DNL (b) INL 49
Figure 3-13 SFDR versus output impedance for single-ended and
differential DACs (a) Single-ended DACs (b) Differential DACs 50
Figure 3-14 The transfer curve of ideal DAC, DAC with FOIE and its
end-point line in differential case 52
Figure 4-1 Architecture of 12-bit DAC with OIC and DEM algorithm 54
Figure 4-2 4-bit LFSR 56
Figure 4-3 (a) Switch controller circuit (b) Truth table of switch controller 57
Figure 4-4 Shift generator 58
Figure 4-5 Architecture of shift circuit 59
Figure 4-6 Simulation results of shift circuit 60
Figure 4-7 Switch Driver Architecture 61
Figure 4-8 The illustration of current-splitting 62
Figure 4-9 Illustration of RTZ circuit 63
Figure 4-10 Floorplan of 12-bit DAC 64
Figure 4-11 The layout view of unit current source 65
Figure 4-12 Layout of the whole DAC chip 66
Figure 4-13 Post-layout simulation of DAC (a) without OIC (b) with OIC 67
Figure 5-1 Post-layout simulation at SF corner of a) shift circuit, b) shift generator 69
Figure 5-2 Pre-sim of a 12-bit DAC with OIC
(Fin=1MHz@Fs=100MHz) (a)Before OIC (b) After OIC 70
Figure 5-3 Pre-sim of a 12-bit DAC with OIC
(Fin=49MHz@Fs=100MHz) (a)Before OIC(b) After OIC 71
Figure 5-4 SFDR vs. Fin curves 72
Figure 5-5 Equivalent circuit of a ferrite bead 73
Figure 5-6 Bypass capacitors in parallel 74
Figure 5-7 Power supply and ground lines setup 74
Figure 5-8 Termination of digital input and clock of DAC chip 75
Figure 5-9 The configuration of DAC output 75
Figure 5-10 Measurement environment setup 76

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