臺灣博碩士論文加值系統

熔絲(fuse)和反熔絲(antifuse)為電子產品中之重要的元件，其功能可做為備用記憶體(Redundancy Memory)，使用於射頻電路(RF)中，及使用於安全碼(Security Code)。電子標籤之較少字碼(Low Bit Count)的資料儲存。傳統上熔絲(Fuse)以金屬熔絲(Metal Fuse)及複晶矽熔絲(Poly Fuse) 為主，寫入方式以大電流于以燒斷，此方式耗耗功率較大。而反熔絲(Anti-fuse)的結構在兩平行板導體間加入介電層，寫入時在兩導體端加一高偏壓使該介電層崩潰，此元件製造在現有的製程上需增加製程步驟。隨著元件尺寸變小，閘極氧化層的崩潰電壓隨著厚度變薄而下降，近年來已有少數公司發展出以MOS元件作反熔絲元件，這類元件寫入方式以閘極氧化層崩潰機制和穿透(punch through)機制為主。
本篇論文利用汲極端穿透機制使得汲極(Drain)到源極(Source)之通道產生永久性損壞，而成為寫入的操做方式。從實驗結果可發現用穿透機制來寫入元件比傳統上用閘極氧化層崩潰所需的寫入電壓低並能縮短寫入時間。本論文亦利用TSUPREM4 及MEDICI 分別去模擬一次寫入型記憶體元件的結構其基本電性，以及元件寫入之狀態

Fuse and antifuse devices are important micro-electric devices. Their applications include as memory redundancy, RF circuit trimming, security code, and low-bit-count electric label. Their device structures of fuse devices are mainly metal fuse-type and poly fuse-type. They can be programmed by applying large current to melt the conductor line, and the power consumption of these programming devices is large. The structure of antifuse devices is two conductor plate sandwiched with thin dielectric material. The high voltage is supplied between two plates at programming. These devices require additional process steps. The commercial antifuse products become feasible since the gate oxide breakdown voltage is decreasing with the device shrinking. The standard MOSFET is used here for study of antifuse devices. The gate oxide breakdown mechanics and avalanche breakdown mechanics can be used for programming
In this thesis, punch-through mechanics are used for programming wherein the high field causes permanently channel breakdown between source and drain terminal. The programming time and programming voltage are decreased based on this programming method. TCAD tools, TSUPREM4 and MEDICI, are used to simulate the antifuse structure, basic electrical characteristics and program behavior.

中文摘要………………………………………………………………... I
Abstract…………………………………………………………………II
致謝…………………………………………………………………….III
Content……………………………………………………………..…..IV
Figure caption...………………………………………………………VII
Table caption…………………………………………………………... X
章節摘要
第一章 非揮發性記憶體及一次寫入型記憶體回顧…………………XI
第二章 金氧半場效電晶體的崩潰機制……………………..………XII
第三章 新型一次寫入型記憶體之量測結果與特性分析………….XIII
第四章 新型一次寫入型記憶體之量測與模擬比較…………….…XIV
第五章 總結與未來工作………………………………………….….XV
Chapter 1 An Overview of Non-Volatile Memory .............................. 1
1-1 Introduction of Non Volatile Memory (NVM) ......................... 1
1-2 Category of the One Time Programmable (OTP) Memory........3
1-3 Variety of the Fuse and Anti-Fuse OTP…...…………………...6
1-4 Variety of the Fuse and Anti-Fuse OTP…...…………………..10
1-5 Organization of This Thesis………..………………………… 12
Chapter 2 Breakdown Mechanism in MOSFET…………………… 13
2-1 Introduction ………………………………………………….. 13
2-2 Gate Oxide Breakdown………………………………………. 13
2- 2. 1 AHI Model……………………………………………15
2- 2. 2 Thermochemical Model………………………………16
2- 2 .3 HR Model……………………………………………..19
2- 2. 4 Channel Hot-Carriers………………………………....19
2-3 Junction Breakdown……………………………….................. 20
2- 3. 1 Thermal Instability……………………………………20
2- 3. 2 Tunneling Effect………………………………………20
2- 3. 3 Avalanche Multiplication……………………………..22
2-4 Punch-Through………………….. …………………………....24
Chapter 3 Characteristic of Anti-Fuse Device …………………….. .26
3-1 The Fabrication of Anti-Fuse Device………………….…26
3-2 Operation Conditions of the Antifuse Devices…….……30
3-2.1 Programming………………………………………30
3-2.2 Read….…………………………………………….32
3-3 Characterization of Anti-Fuse Device…………………..34
3-4 Reliability Analysis……………………………………..42
3-4.1 Read Disturb………………………………………42
3-4.2 Data Retention……………….…………………....43
3-5 Conclusions…………………….…………………........43
Chapter 4 Simulation of Anti-Fuse Device………………………......45
4-1 Simulation of Anti-Fuse Device…………..……………..45
4-2 Comparisons between Simulation and Measurement……58
4-3 Summary………………………………………………....60
Chapter 5 Conclusion and Future Work……………...…………......61
5-1 Conclusions…………………………………..…………..61
5-2 Future works…………………………………………..…61
Reference ……………………………………………………………...62
Autobiography……………………………………………………..….65

Figure Captions

Figure 1-1: The cross section of anti-fuse
Figure 1-2: The cross section of poly–diffusion anti-fuse with an oxide–nitride–oxide (ONO) dielectric
Figure 1-3: The cross section of metal–metal anti-fuse (ViaLink)
Figure 2-1: Formation of traps in the gate-oxide
Figure 2-2: Creation of conduction path through traps in the gate-oxide
Figure 2-3: Increased traps in the gate-oxide after conduction
Figure 2-4: Cross section of the gate-oxide after hard breakdown
Figure 2-5: SiO2 bond breakage due to hole current
Figure 2-6: Chemical structure of SiO2
Figure 2-7: Oxygen vacancy in SiO2
Figure 2-8: Local electric field in SiO2
Figure 2-9: The hole trap in SiO2
Figure 2-10: Parasitic bipolar transistor action.
Figure 3-1: The schematic process flow of the anti-fuse device
Figure 3-2: Fig 3-2: It shows illustrate of current flows in the antifuse during the programming.
Figure 3-3: Fig 3-3: The ID-VG curves at initial and programming state.
Fig 3-4: The ID-VD curves at programmed state
Fig. 3-5: The ID-VG curve of the antifuse is at initial condition.
Fig. 3-6: The ID-VD curve of the antifuse is at initial condition.
Fig 3-7: The Isub, ID and IG measuring result of all standard n-MOSFET
Figure 3-8: Breakdown characteristics of an n-channel MOSFET. The bottom curve corresponds to VG=0V and step for VG is 0.5V.
Figure 3-9: Plot of breakdown voltage at different gate voltage.
Figure 3-10: Program disturb at VG=0 VD=9.0V and VG=0V VD=8.5V, while source and gate are 0V.
Figure 3-11 (a) Programming speed at VG=1.5V. Fig 3-11 (b) Programming speed at VD=8V.
Figure 3-12: (a): Read current distribution of initial cells Read current ID at VG=0V VD=1V (b): The read current distribution of programmed cell after a VD=8.0V VG=1.5V 1us programming pulse. Read current ID at VG=0V VD=1V
Figure 3-13: program time dispersion. The programming is succeed while drain current is large than 100uA at VD=1V
Figure 3-14: Read disturb experiment at VD=1V. Read current is measurement at 1V.
Figure 3-15: (a)Program and initial antifuse cell read current shift versus back time at 25℃ (b) Program and initial antifuse cell read current shift versus time at 250℃
Figure 4-1 The simulated the NMOSFET cross sections view
Figure 4-2 The simulated ID-VG curves.
Figure 4-3 The simulated ID-VD curves.
Figure 4-4 (a) The 2-D potential distribution of the anti-fuse at VG=1.5, VD=8.0V(b) The 2-D Electron distribution of the anti-fuse at VG=1.5, VD=8.0V(c) The 2-D Hot carrier generation of the anti-fuse at VG=1.5, VD=8.0V (d) The 3-D electron concentration of the anti-fuse at VG=1.5, VD=8.0V(e) The 3-D electron Field of the anti-fuse at VG=1.5, VD=8.0V(f) The 3-D hot carrier generation of the anti-fuse at VG=1.5, VD=8.0V(g)The 1-D lateral electron field and hot carrier generation of the anti-fuse at VG=1.5, VD=8.0V(h) The 1-D vertical electron field and hot carrier generation of the anti-fuse at VG=1.5, VD=8.0V
Figure 4-4 (a) The 2-D potential distribution of the anti-fuse at VG=0, VD=8.0V(b) The 2-D Electron distribution of the anti-fuse at VG=0, VD=8.0V(c) The 2-D Hot carrier generation of the anti-fuse at VG=0, VD=8.0V (d) The 3-D electron concentration of the anti-fuse at VG=0, VD=8.0V(e) The 3-D electron Field of the anti-fuse at VG=0, VD=8.0V(f) The 3-D hot carrier generation of the anti-fuse at VG=0, VD=8.0V(g)The 1-D lateral electron field and hot carrier generation of the anti-fuse at VG=0, VD=8.0V(h) The 1-D vertical electron field and hot carrier generation of the anti-fuse at VG=0, VD=8.0Vvc
Fig 4-6 The ID-VG of the anti-fuse at VD=0.1V
Fig 4-7(a) The ID-VD of the anti-fuse at VG=0V (b) The ID-VD of the anti-fuse at VG=0.5V(c) The ID-VD of the anti-fuse at VG=1V-3V.

Table Captions

Table3-1: Programming at different bias.
Table 4-1: The process parameters for the Tsuprem-4 simulation
Table 4-2: Operation condition

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