臺灣博碩士論文加值系統

訊號在傳輸時，可能受到雜訊的影響，造成信號的失真，進而降低電路效能。雜訊來源除了有可能來自其他系統，也有可能系統本身內部產生。本論文首先探討各項雜訊的來源，並且建立基板模型以及電源模型，接著在力晶高壓製程上，完成了抗雜訊電路，其中包含有雜訊選擇、雜訊源以及抗雜訊系統。驗證方式分為兩種，首先藉由雜訊源產生的內部雜訊，紀錄有無抗雜訊系統下，基板雜訊以及電源雜訊大小的差異。另一種驗證方法為利用偏壓器來輸入外部雜訊，觀察雜訊抑制的情況。最後藉由雜訊計算公式，計算出雜訊抑制情況大約為40%左右。 其次，實現5.8G低雜訊放大器於0.35um CMOS製程上，並且結合主動電感以及抗雜訊應用。使用主動電感目的為降低晶片面積進而減少成本，抗雜訊應用則為降低低雜訊放大器的雜訊指數，讓電路有更好的效能。最後得到具有輸入匹配為-11dB、輸出匹配為-11dB、增益為18dB、雜訊指數為2.8dB、IIP3約為-4dBm、功率消耗為25mW的5.8G低雜訊放大器 最後實現8-12G的X頻段寬頻放大器，使用90nm CMOS製程並下針量測。電路設計為電阻並聯回授式並採用雜訊抵消方法降低放大器內部雜訊，即可降低低雜訊放大器的雜訊指數。量測結果得到在8-12G頻帶內，輸入匹配為-10dB以下，輸出匹配為-10dB以下，增益大約為11dB左右，雜訊指數為2.5-4，IIP3則為-7dBm左右，功率消耗為8mW的低雜訊放大器。

Noise usually causes signal distortion, thus degrading the circuit performance. In this thesis we discuss various sources of noise and the models of the substrate and power line at first. Then, a noise decoupling circuit is implemented using the PSC (Powerchip Semiconductor Corp.) high voltage process. The circuit has noise select, noise sources and the noise decoupling system. There are two types of experiments. First, on-chip noise sources are used to generate the internal noise. The magnitude of the substrate noise and power noise are measured with the noise decoupling system activated or deactivated. Then an external noise is applied through bias-T to observe the efficiency of noise suppression. There is about 40% reduction of noise. Secondly, a 5.8G low noise amplifier with an active inductor and noise decoupling system is implemented using 0.35um CMOS process. An active inductor is adopted to reduce chip area and costs. As to noise decoupling, it could reduce the noise figure of the LNA, so the circuit has better performance. The LNA exhibits input matching less than -11 dB, output matching less than -11 dB, 18 dB gain, 2.8 dB noise figure, -4 dBm IIP3, and 25 mW power consumption. Finally, an 8-12 GHz X-band broadband amplifier is implemented using 90 nm CMOS process. On-chip probing is used to measure the performance of the LNA. A shunt-feedback resistor and noise cancellation method are used in the amplifier designed to lower the noise figure. The LNA exhibits input matching less than -10 dB, output matching is less than -10 dB, 11dB gain, 2.5~4 dB noise figure, -7 dBm IIP3, and 8 mW power consumption.

致謝ii
口試委員審定書iii
中文摘要v
英文摘要vi
第一章 緒論1
第二章 雜訊模型及抗雜訊系統2
2.1簡介2
2.2 基底與電源雜訊模型的建立.6
2.3主動抗雜訊系統概念8
2.4架構實現10
2.5抗雜訊電路量測結果與討論14
第三章 低雜訊放大器設計原理26
3.1 簡介 26
3.2 基本概念27
3.2.1 S參數(s-parameter)與電路匹配(matching)28
3.2.2雜訊指數(noise figure, NF)29
3.2.3 穩定度(stability)31
3.2.4 1dB壓縮點(1dB compression point)32
3.2.5 輸入三階截斷點(input third-order intercept point, IIP3)33
3.3 低雜訊放大器基本電路架構34
第四章 低雜訊放大器耦合主動電感與抗雜訊系統36
4.1 主動電感簡介36
4.2 主動電感電路分析37
4.3 電路實現39
4.4 抗雜訊低雜訊放大器量測結果45
第五章 具抗雜訊寬頻低雜訊放大器51
5.1 簡介51
5.2 寬頻低雜訊放大器架構52
5.3 抗雜訊技術概念55
5.4電路實現結果57
5.5 量測結果58
第六章 結果與討論64
參考文獻65

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