臺灣博碩士論文加值系統

隨著製程的演進，電路系統的工作電壓也越來越低，對數位電路來說，當工作電壓越低，能夠在相同的電路功能下有更低的消耗功率，這在手持式電子商品已成為主流的現在，降低工作電壓來節省功率消耗無疑是未來的趨勢。但對於類比電路而言，較低的工作電壓，帶來的不單單是效能的降低，很多原本實用的電路架構，在低工作電壓下根本無法正常作動，因此如何創新電路設計，來使類比電路在低電壓環境下仍能有著相同甚至更好的效能，就成為類比電路設計一個熱門的課題。
本論文提出兩種改善三極區轉導放大器線性度的方法。並分別達成了高轉導值調整範圍、低工作電壓以及高線性訊號輸入範圍，並且兩者的消耗功率都極低。第一種是將輸入對電晶體偏壓在三極區，並加入一組弱反轉區輸入對，以抵消第三階諧波失真，其工作電壓為1.2V並消耗功率0.226mW。當輸入信號頻率為0.4Vpp時，可達成第三階諧波失真-71.3dB。此轉導放大器是以台積電0.18μm CMOS 1P6M 製程實現，使用面積為 。
第二種轉導放大器也是將輸入對電晶體偏壓在三極區，並加入了高效能的遷移率補償機制，成功壓低了22.4dB的第三階諧波失真。其工作電壓為1.8V並消耗功率427mW。當輸入信號頻率為1.2Vpp時，可達成第三階諧波失真-79dB。此轉導放大器是以台積電0.18μm CMOS 1P6M 製程實現，使用面積為 。

With the evolution of the fabrication technology, the supply voltage of the electric circuit systems has become lower and lower. Since portable electronic devices are getting very popular, it is the trend to lower power supply voltage in order to decrease power consumption. For digital circuits, when the power supply reduces, the power consumption would be lower while circuit performance stays the same. However, for analog circuits, the low voltage supply might not only bring the downgrade of circuit performance, but also cause failure of some basic circuit structures. It has attracted lots of attentions to design analog circuits to work under low voltage conditions.
Two circuits have been proposed to improve the linearity of the transconductors working in the triode region. High transconductance tuning range, low voltage supply, and high linearity are all achieved in the design. The first circuit is designed by biasing input transistor pair in the triode region, in parallel with another input pair working in the weak inversion region, to cancel out the third order harmonic distortion. The power supply voltage is 1.2V and the circuit consumes 0.226mW. The third order harmonic distortion of -71.3dB is achieved with the input signal of 0.4Vpp. The transconductor fabricated by TSMC 0.18um CMOS 1P6M technology occupies the area of .
The second transconductor also biases the input transistor pair in the triode region. In addition, high performance mobility compensation mechanism has been implemented. It has successfully suppressed the third order harmonic distortion by 22.4dB. The supply voltage is 1.8V and the circuit consumes 427uW. The third order harmonic distortion of -79dB is achieved with the input signal of 1.2Vpp. The transconductor fabricated by TSMC 0.18um CMOS technology occupies the area of .

摘 要 I
目錄 VI
圖目錄 VIII
表目錄 X
第 一 章 緒 論 1
1.1 研究動機 1
1.2 論文組織 2
第 二 章 轉 導 放 大 器 3
2.1 緒論 3
2.2 CMOS製程之高線性轉導放大器的基本架構 3
2.2.1 全差動輸入對 (Fully Differential input pair) 3
2.2.2 偽差動輸入對 (Pseudo-differential input pair) 6
2.2.3 源極退化差動輸入對 (Source degeneration differential pair) 8
2.2.4 改良式源極退化差動對 (Modifier Source degeneration differential pair ) 9
2.2.4.1 使用運算放大器的源極退化差動對 (Source degeneration differential pair with OP amp.) 10
2.2.4.2 使用電壓隨耦器的源極退化差動對 (Source degeneration differential pair with FVF) 11
2.2.5 三極區電晶體輸入對(Triode transistor input pair) 12
2.2.6 並聯式差動對(Multiple differential-pairs) 14
2.3 遷移率降低補償 (Mobility reduction compensation) 15
2.3.1 利用弱反轉區來補償遷移率降低 16
2.3.1.1 利用弱反轉區來補償偽差動輸入對之遷移率降低 17
2.3.1.2 利用弱反轉區來補償三極區輸入對之遷移率降低 19
2.3.2 利用三極區來補償飽和區輸入對之遷移率降低 20
第 三 章 高線性度三極區轉導放大器 22
3.1 緒論 22
3.2 低工作電壓、低功耗、高線性度之三極區轉導放大器 22
3.2.1 低功耗轉導放大器架構介紹 22
3.2.2 線性度提升 25
3.2.3 共模回授與共模前授電路 28
3.3 高輸入範圍且高線性的低功耗轉導放大器 29
3.3.1 轉導放大器架構介紹 30
3.3.2 非線性項改善 32
3.3.3 共模回授與共模前授電路 38
3.3.4 雜訊分析 39
第 四 章 模 擬 與 量 測 41
4.1 緒論 41
4.1.1 總諧波失真 (THD) 41
4.1.2 第三階諧波失真 (HD3) 42
4.1.3 共模拒斥比 (CMRR) 43
4.1.4 電源供應拒斥比 (PSRR) 43
4.1.5 功率 (Power) 43
4.2低工作電壓、低功耗、高線性度之三極區轉導放大器性能參數 45
4.2.1 模擬結果 45
4.2.2 佈局圖與量測結果 49
4.2.3 性能總結 51
4.3高輸入範圍且高線性的低功耗轉導放大器之性能參數 53
4.3.1 模擬結果 53
4.3.2 佈局圖 57
4.3.3 性能總結 58
第 五 章 結 論 59
5.1結論 59
5.2 未來展望 59
參考文獻 61

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