臺灣博碩士論文加值系統

信號抖動(Signal Jitter)對許多裝置而言；是一項不可不正視的問題。隨著科技的日新月異，人們對許多設備的精凖度與速度的要求也愈來愈高，這當中信號抖動有無妥善的處理即扮演著一個重要角色。長久以來，全世界的學術界與工程師們，均著重於探討時序信號抖動(Clock Jitter)的量測與其對電路的影響，甚少有人去觸及電路設計和資料信號抖動(Data Jitter)的問題，資料信號抖動一樣會對裝置造成不穩定因素，而同時去解決這兩種信號抖動的電路設計更是有如鳳毛麟角，本論文即是同時處理時序信號抖動與資料信號抖動，並在輸出時使兩者同步。

本論文利用時序信號固定的週期關係產生單一(Mono-Stable)脈波來對積分器(Integrator)積分，所產生的積分波(Sawtooth Wave)與在比較器(Comparator)上的固定參考電壓(Reference)作比較，此時；積分波和參考電壓會有交叉點(Intersection)產生，利用此一交叉點作為觸發信號，使已被消除jitter成份的脈波信號還原成時序信號原有的週期關係。再以正確的時序信號做T型正反器的時脈，調整資料信號的延遲時間使其稍為超前時序信號，讓資料信號的正緣(Rising Edge)與負緣(Falling Edge)各產生單一脈波，隨後；同時送入正反器來消除抖動並同步輸出。經由電路模擬實驗證實可以有效地消除隨機抖動(Random Jitter)、週期性抖動(Period Jitter)、相對性週期抖動(Cycle-to-Cycle Jitter)和累積性抖動(Long-Term Jitter)。

Signal jitter is an important factor that has no way to ignore many circuit. Solving signal jitter becomes the essential work when facing the mechanism requirement of precision and speed from users. Researches in this field are devoted to the measurement of clock jitter and its influence on circuits, so far. Fewer of them are focused on the analysis and the corresponding effect of data jitter, which can be the unstablization factor of a mechanism, on circuits; even the researches of concerning both of these two kinds of jitters. This research focuses on processing these two kinds of jitters simultaneously and synchronizing the outputs of both.

First of all, a mono-stable pulse is generated based on a fixed clock cycle for the integration computing with integrator. The intersection occurred when comparing the output sawtooth wave with the reference fixed voltage from the comparator. And the trigger signal referred to the intersection help to return the jitter removed of pulse signals to cycles of the original clock signals. T flip-flop treats the correct clock signals as its pluses and tunes the time lags from signals for lightly overtaking signals. It allows each of the rising edge and the falling edge of signals generates a mono-stable pulse, and input them to T flip-flop for removing jitters and synchronizing outputs. Experiments conducted with simulated data show our proposed circuit decreases effectively random jitters, period jitters, cycle-to-cycle jitter and long-term jitters.

第一章 緒論 .............................................. 1
第一節 研究背景 .................................... 1
第二節 研究動機 .................................... 2

第二章 相關背景 .......................................... 3
第一節 Jitter的定義 ............................... 3
第二節 Jitter的種類 ............................... 4
第三節 Jitter的統計分析 ........................... 9
第四節 時間/相位轉換原理 .......................... 11

第三章 系統原理說明及驗證 ............................... 13
第一節 系統方塊圖 ................................. 13
第二節 電路原理說明 ............................... 14
第三節 電路串疊架構 ............................... 22
第四節 電路設計規則 ............................... 24
第五節 系統功能驗證 ............................... 28

第四章 結論 ............................................. 39
第一節 總結 ....................................... 39
第二節 未來方向 ................................... 41

參考文獻 ................................................. 42

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