臺灣博碩士論文加值系統

本論文的目的在於實現CMOS位移電容感測器之佈局，並比較佈局前後效能之差異。文中利用雙級運算放大器做為主體，接著佈局離散元件，並在佈局後些微修改以達到需求，最後探討全系統架構模擬之電容改變量與輸出電壓間的關係，本系統模擬後解析度可達 法拉等級。
而本論文使用國家晶片系統設計中心(NSC Chip Implementation Center, CIC)所提供的台灣積體電路(TSMC)0.35μm Mixed-Signal 2P4M Polycide 3.3/5V的製程，並使用Synopsys 公司所出的Hspice電路模擬軟體與思源公司的laker軟體進行模擬及佈線。

The purpose of this dissertation is to realize the design and layout of CMOS capacitive sensing circuit, and in this case to compare the differences before and after layout. In this dissertation use the two-stage amplifier to be the principal. Furthermore, layout the dispersed elements, and modify that after layout to satisfy our requirement.
This dissertation is applying 0.35μm Mixed-Signal 2P4M Polycide 3.3/5V manufacture process of TSCM which is provided by NSC Chip Implementation Center. Finally, using Hspice software designed by Synopsys co. to simulate and laker software designed by Springsoft co. to layout.

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 IX
第一章 導論 1
1.1 研究背景 1
1.2 研究動機與目的 2
1.3 文獻回顧 3
1.4 本文目的與章節摘要 8
第二章 環形陀螺儀之振動原理與分析 10
2.1 環形陀螺儀之原理簡介 10
2.2 環狀陀螺儀感測原理 12
2.3 環形陀螺儀架構與電容值計算 12
2.4 本論文架構電容值的估算 14
第三章 系統架構與運算放大器佈局與模擬 16
3.1 本論文電路之系統架構 16
3.2 雙級運算放大器架構 17
3.3 雙級運算放大器之佈局 19
3.4 雙級運算放大器之特性模擬 21
第四章 離散元件之佈局與模擬 28
4.1 前言 28
4.2 取樣與保存(Sample and Hold) 28
4.3 無穩態多諧振盪器 29
4.4 緩衝器(Buffer) 34
4.5 S/H之時脈設計(Clock Design) 36
4.6 本章綜合結果 40
第五章 模擬結果 41
5.1 前言 41
5.2 單一運算放大器模擬結果 42
5.3 差動放大器模擬結果與改良 45
5.4 全電路系統模擬 49
5.5 感測電容訊號與輸出弦波訊號之關係 57
5.6 佈局後系統效能降低原因之探討 61
第六章 結論與未來展望 63
參考文獻 64
附錄A CMOS佈局設計之簡介 67
附錄B 雙級運算放大器之細部設計 71
附錄C 連線電容 83
附錄D 電阻之佈局設計 89
附錄E 折疊疊接放大器之設計 92

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