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研究生:簡元德
研究生(外文):Yuan-Te Chien
論文名稱:Class E功率放大器和可調偏壓式功率放大器以及變壓器結合放大器
論文名稱(外文):Research of CMOS Class E Power Amplifier, Adaptive Bias Power Amplifier and Transformer Combined Power Amplifier
指導教授:黃天偉
指導教授(外文):Tian-Wei Huang
口試委員:張嘉展蔡政翰莊晴光
口試日期:2012-07-13
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電信工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:129
中文關鍵詞:金氧半場效電晶體功率放大器自調偏壓式
外文關鍵詞:CMOS TransistorPower AmplifierAdaptive Bias
相關次數:
  • 被引用被引用:0
  • 點閱點閱:634
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  • 收藏至我的研究室書目清單書目收藏:0
這幾年隨著無線通訊的成長,為了有更高的傳輸速率,更遠的傳輸距離,或者更可靠的傳輸方式,需要一個可以整合的解決方法。而功率放大器便是其中一個重要的瓶頸。傳統上,3-5族高電子移動率電晶體,例如砷化鎵,擁有高輸出功率以及高功率附加效率。使用互補式金氧半電晶體製作功率放大器,有其一定的限制跟困難,但為了系統整合以及小尺寸,製作於互補式金氧半導體製程上的功率放大器日漸重要,也引起了越多人的研究。
在本論文中,我們設計了兩顆操作於Class E mode 的功率放大器使用的是TSMC 180nm CMOS process. 第一顆功率放大器有8-dB的增益, 40%的功率附加效益還有15dBm的飽和輸出功率在5.8GHz。 第二顆功率放大器有超過20dB的增益,50%功率附加效益還有20dBm的飽和輸出功率在2.4GHz。 第三顆電路為自我調整偏壓是功率放大器,使用的是TSMC 180nm CMOS process。 第四顆電路為使用變壓器結合的功率放大器,使用的也是TSMC 180nm CMOS process。


The growth in wireless communication has strong demands in integrated solution to have faster transmission speed, more distance, and more reliable transmission. Power amplifier is one of the bottlenecks. Traditionally, Ⅲ-Ⅴ high electron mobility transistor, ex. GaAs has the high output power and high power added efficiency. It has certain restrictions and difficulties about using complementary metal-oxide semiconductor to design the power amplifiers. For the reason of system integration and small area to cost down, the fabrication of power amplifiers using complementary metal-oxide semiconductor arises attention gradually and more and more researchers study relevant topics.
In this thesis, we design two circuits in Class E Power Amplifier operation using 180nm CMOS processes. The first power amplifier achieves 8-dB small signal gain, 40% PAE, and 15 dBm output saturation power at 5.8GHz. The second power amplifier achieves 20-dB small signal gain, 50% PAE, and 20 dBm output saturation power at 2.4GHz. The third circuit is Adaptive Bias Power Amplifier using 180nm CMOS processes. The fourth circuit is Transformer Combine Power Amplifier using 180nm CMOS processes.


口試委員會審定書 #
誌謝 i
中文摘要 ii
ABSTRACT iii
CONTENTS iv
LIST OF FIGURES vii
LIST OF TABLES xiii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Contributions 2
1.3 Thesis Organization 2
Chapter 2 Introduction to Power Amplifiers 4
2.1 Introduction 4
2.2 Performance metrics of power amplifiers [1][2] 4
2.2.1 Linearity of Power Amplifiers 4
2.2.2 Inter-Modulation ratio (IMR) & Intercept Point 6
2.2.3 Power Amplifier Efficiency 10
2.3 Classifications of the Power Amplifiers [1] 10
2.3.1 Class-A Power Amplifier 11
2.3.2 Class-B Amplifiers 13
2.3.3 Class-AB Amplifier 15
2.3.4 Class-C Amplifier 15
2.3.5 Class-E Amplifier 16
2.3.6 Class-F Amplifier 16
Chapter 3 5.8GHz & 2GHz CMOS Class E Power Amplifier 18
3.1 Introduction 18
3.2 Class E Operation 20
3.3 Process Basis 27
3.4 Design of 5.8 GHz Class E Amplifier 28
3.5 Simulation Results & Layout 33
3.6 Measurement Results 37
3.7 Design of a 2 GHz Class E Amplifier 43
3.8 Simulation Results 49
3.9 Measurement Results 51
3.10 Summary 53
Chapter 4 A 24GHz CMOS Adaptive-Bias Power Amplifier 56
4.1 Introduction 56
4.2 Process Basics 57
4.3 Previous Work 58
4.4 Design of a 24GHz power amplifier 60
4.5 Simulation Results 86
4.6 Measurement Results 89
4.7 Summary 92
Chapter 5 A 5.8GHz Transformer Combined Power Amplifier 94
5.1 Introduction 94
5.2 Previous Work 95
5.3 Design of a 5.8GHz power amplifier 96
5.4 Simulation Results 112
5.5 Measurement Results 117
5.6 Summary 119
Chapter 6 Conclusions 122
REFERENCE 124


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