臺灣博碩士論文加值系統

本論文是研究靜電放電 (electrostatic discharge) 所產生之高電場和高電流脈衝對金氧半元件 (metal-oxide-semiconductor device) 的效應，其包含氧化層陷阱和界面陷阱密度、空間分布以及崩潰電場特性，並與直流應力效應做比較和探討，進而提出靜電放電應力所產生陷阱和崩潰的機制。根據實驗結果，靜電放電會引發氧化層局部性的絲狀電流導通，而氧化層界面的粗糙或局部變薄現象會更惡化此現象，最後導致比直流應力更提前的氧化層崩潰。並且，高電場應力會造成氧化層邊界陷阱的不均勻分布，進而產生金氧半元件參數的嚴重漂移和退化。 研究結果顯示，直流應力會產生大量的邊界和界面陷阱，以及快速飽和的氧化層陷阱；而靜電放電應力則產生較少量的邊界和界面陷阱，以及持續增加的氧化層陷阱。在高電場電流脈衝的累積 (accumulation) 應力作用之下，帶正電的氧化層陷阱會增強外加電場進而加速氧化層的退化；然而邊界陷阱會因為跟隨不上快速變化的電場而無法釋放電荷，因而產生抵銷電場並減小外加電場的效應，減緩氧化層的退化。所以，邊界陷阱和帶正電的氧化層陷阱在高頻率的應力作用之下，其對Fowler-Nordheim 應力電流的效應是相反的。因此，若預先將氧化層做直流應力，則其氧化層的靜電放電崩潰電壓會出現反轉的特性，因為有大量的邊界和界面陷阱以及快速飽和的氧化層陷阱的關係。另一方面，若預先將氧化層做靜電放電應力，則其後的氧化層靜電放電崩潰電壓會隨著預先應力的增加而持續變小，這是因為靜電放電預應力產生較少量的邊界和界面陷阱以及持續增加的氧化層陷阱的關係。故相對於直流預應力的效應，靜電放電預應力對半導體元件和產品的靜電放電耐受能力會產生嚴重的退化問題。 其次，在薄氧化層的靜電放電崩潰機制方面，實驗結果發現，不論是直流應力或是靜電放電應力，氧化層陷阱的產生皆是因為陰極的熱電子經由價帶穿隧至傳導帶所產生撞擊離子化 (band-to-band impact ionization) 效應所造成的。其引發崩潰的氧化層陷阱的密度和分布是相近的。此結果與先前眾多論文發表的機制是相同的，即電洞先於陽極產生，進而因電場作用漂移到陰極附近，最後引發氧化層的崩潰。然而，在厚氧化層的靜電放電崩潰機制方面，氧化層陷阱的密度和分布對直流應力和靜電放電應力是完全不同的。直流應力產生的熱電子靠氧化層陷阱的幫助而穿隧至傳導帶並產生撞擊離子化 (trap-assisted impact ionization) 效應，造成更多的氧化層陷阱和退化，其整體氧化層陷阱所表現的電性是負的；而靜電放電應力則是產生較高能量的熱電子，經由價帶穿隧至傳導帶所產生撞擊離子化效應，而產生氧化層陷阱和退化。與直流應力相比，靜電放電應力產生較少的帶負電氧化層陷阱，並且最終帶正電氧化層陷阱的數目會多過帶負電氧化層陷阱的數目。這是因為靜電放電應力引發較高的電場電流，並且局部的在穿隧距離附近產生氧化層陷阱，與直流應力相比，這些能量較高的陰極入射電子產生帶正電氧化層陷阱的效率較高，並且在比較低的陷阱密度下引發氧化層的崩潰。 另外，關於界面陷阱分布的實驗結果顯示，靜電放電應力在氧化層中所產生之界面陷阱的數目遠小於直流應力效應，且其界面陷阱在電晶體通道方向上的分布狀況，顯示
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出比直流應力效應更高的局部性和不均勻性。因此，在靜電放電應力的作用之下，氧化層界面的粗糙或變薄現象會增強其局部有效電場，並且強化載子撞擊及累增 (avalanche)效應，進而產生大量且集中的界面陷阱，最後導致比直流應力更提早的氧化層崩潰。最後，在界面陷阱分布的進一步研究結果中顯示，不均勻的氧化層邊界陷阱會造成低頻的電容電壓特性曲線變形，而此變形可以成功的用不同損壞程度的氧化層的電容電壓特性曲線來組合模擬和驗證。並且，低頻率電荷激發 (charge pumping) 量測的結果亦顯示出氧化層邊界陷阱不均勻分布所造成的雙峰現象，其產生機制應是平帶 (flat-band) 和臨限 (threshold) 電壓的分裂所造成。當電晶體面對高電場應力時，短通道電晶體會產生更嚴重的邊界陷阱不均勻現象，造成金氧半元件參數的漂移和退化，嚴重影響類比電路的精確性和功能。

The effects of ESD high-field current impulse on gate oxide and made comparisons with the results of dc stress is studied in this thesis. Including generation of stress-induced trapped charges and the breakdown mechanisms were proposed. Besides, the density and spatial distribution of traps by ESD and dc stressing were investigated. According to the centroid of oxide trapped charges and the profile of interface traps induced by ESD stress, the explanation for locally filamentary current conduction and early oxide breakdown are suggested. Finally, lateral non-uniformities of border traps (near interface oxide traps) can lead to serious distortions of both C-V curve and charge-pumping signal, which may induce serious drift and degradation of the parameters of metal-oxide-semiconductor (MOS) devices. With respect to the formation of stress-induced traps in gate oxide, dc stress induces a large number of border traps and fast saturated positive oxide traps, whereas ESD stress generates less border traps and the increasing positive oxide traps. Under accumulation mode impulse stress, the positive oxide trapped charges can increase the applied electric field and deteriorate the oxide degradation during stressing, while border traps fail to de-trap charges and decrease the applied field near the interface and retard the oxide degradation due to the disabled response to the fast change of electric field. The effects between positive oxide traps and border traps on Fowler-Nordheim stress current are tradeoff during high frequency stress. Therefore, ESD emulation by TLP (transmission line pulsing) reveals a turn-around phenomenon of oxide breakdown characteristics under dc pre-stress. However, under TLP impulse pre-stress, the degradation continues increasing as the number of TLP pre-stress impulses increases. An impulse pre-stress thus appears to be a highly critical issue for the ESD immunity in devices and products. As for the breakdown mechanisms of oxide subjected to dc and ESD (TLP) stresses, it was
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observed that for 3.2-nm-thin oxide, the oxide trapped charges are generated by band-to-band impact ionization. The centroid evolution and the critical density of positive oxide trapped charges to trigger oxide breakdown are about the same and these results are consistent with the existing models of stress-induced trapping charges and the hole induced oxide breakdown. However, different behaviors of oxide trapped charges and centroid were found for 14-nm-thick oxides subjected to different stress tests. As compared with dc stress, which induces oxide trapped charges by trap-assisted impact ionization, the TLP impulse stress generates far less amount of oxide trapped charges by band-to-band impact ionization, and the positive oxide trapped charges finally dominates over the negative oxide trapped charges. This impulse stress imposes a high density and transient current on the oxide, induces traps at the tunneling distance locally. The hotter injected electrons generate more efficient hole trappings to provoke breakdown with lower density of oxide trapped charges. Regarding to the spatial distribution of interface traps in silicon dioxide induced by electrostatic discharge high-field current impulse. It was observed that TLP stress induces far less amount of interface traps prior to breakdown and the interface traps distribution along the channel direction is more non-uniform and localized than dc stress. The mechanisms are suggested that under ultra-high-field TLP stressing, the asperities at the electron injecting interface of gate oxide further increase the stress field locally, which enhances a regenerative avalanche process of impact ionization and trap generation. In addition, the lateral non-uniform distribution of trapped charges in stressed gate oxide was investigated. The distortions of low frequency C-V curves are mainly caused by the non-uniform distribution of border traps, which can be successfully simulated by the combination of C-V curves of heavily and lightly damaged regions. Besides, double-peak charge-pumping current is also observed in low frequency measurement. The non-uniform flat-band and threshold voltages are proposed as factors contributing to double-peak signal. And, devices with a shorter channel exhibit a more severe lateral non-uniform damage of gate oxide.

Contents Abstract (in Chinese) ……………………………………………………….…i Abstract (in English) ………………………………………………………... iii Acknowledgement ………………………………………………………….....v Contents …………………………………………………………....................vi Figure Captions …………………………..……………………………........viii Chapter 1 Introduction 1.1 The phenomenon and origin of electrostatic discharge (ESD) ……………..………….…1 1.2 The reliability issues of MOS devices subjected to ESD ………………………………...2 1.2.1 Characteristics of high-current impulse stress…………………………………....3 1.2.2 Oxide degradation due to ESD …………………………………..………………4 1.3 ESD characterization by transmission-line-pulsing (TLP) test system ………………..…5 1.4 Thesis organization …………………………………………………………..…………...5 Figures …………………………………………………………..............................................8 Chapter 2 Effects of ESD High-Field Current Impulse on Oxide Breakdown 2.1 Introduction ………………………………………………...............................................12 2.2 Experiment ……….………………………………………...............................................14 2.3 C-V and I-V properties of MOS capacitors subjected to dc and TLP ..............................15 2.4 Failure distributions of oxide breakdown voltage for TLP impulse stress........................17 2.4.1 Retardation of border trapped charges due to the stress field of TLP impulse ....17 2.4.2 Degradation of oxide breakdown due to the positive oxide trapped charges ......18 2.5 Summary ……….………………………………………..................................................19 Figures ………………………………………………………….............................................20 Chapter 3 Oxide Trapped Charges Induced by ESD Impulse Stress 3.1 Introduction ………………………………………………...............................................28 3.2 Experiment ………………………………………………................................................29 3.3 Oxide trapped charges and centroid in thin-oxide MOS capacitors .................................31 3.3.1 Correlation between current density and electric field of dc and TLP stress ......31 3.3.2 Band-to-band impact ionization to cause oxide trapped charges .........................32 3.4 Oxide trapped charges and centroid in thick-oxide MOS capacitors ...............................32 3.4.1 DC stress effect due to trap assisted impact ionization ........................................32 3.4.2 TLP impulse stress effect due to band-to-band impact ionization .......................34
4.3.2 Analysis of electric field sensitivity …………….................................................45
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3.5 Summary ……….………………………………………..................................................34 Figures ………………………………………………………….............................................35 Chapter 4 Characterization of the ESD induced non-uniform profiling of interface traps in metal-oxide-semiconductor field-effect transistors using charge-pumping technique 4.1 Introduction ………………………………………………...............................................43 4.2 Experiment ………………………………………………................................................44 4.3 Interface trapped charges induced by dc and TLP stress …..............................................45 4.3.1 Quantity and distribution of interface trapped charges in gate oxide ..................45 4.3.3 Asperities enhanced regenerative avalanche process of impact ionization and trap generation ………………………………………...............................................46 4.4 Summary ……….………………………………………..................................................46 Figures ………………………………………………………….............................................48 Chapter 5 Origin of double-peak charge-pumping current due to lateral non-uniformity effect of border and interface traps in metal-oxide-semiconductor field-effect transistor 5.1 Introduction ………………………………………………...............................................52 5.2 Experiment ………………………………………………................................................53 5.3 Double-peak charge-pumping current due to lateral non-uniformity effect of border and interface traps …………………………………………..................................................54 5.3.1 Lateral non-uniformity simulation for low frequency C-V .................................54 5.3.2 Geometric effect on lateral non-uniformity …….................................................56 5.3.3 Double peak charge pumping current at low frequency due to slow border and interface traps …………………………………..................................................57 5.4 Summary ……….………………………………………..................................................58 Figures ………………………………………………………….............................................59 Chapter 6 Conclusion and suggestion for future work 6.1 Main results of this work ……………………………………..........................................66 6.2 Suggestion for future work …………………………………...........................................67 References ……………………………………………………...........................................69

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