臺灣博碩士論文加值系統

微晶矽薄膜電晶體近來已被廣泛的研究，其擁有可大面積低溫成長的優點，且元件特性又優於非晶矽薄膜電晶體，例如，較高的電子移動率及較低的能帶間隙，普遍被認為將來可以取代非晶矽薄膜電晶體在大尺寸液晶顯示器上的應用地位。但微晶矽薄膜電晶體有一些先天上的問題，例如，漏電流過高、製程上的不均勻性，以及與多晶矽薄膜電晶體相比較差的元件特性等。為了增進微晶矽薄膜電晶體之元件特性，本論文將研究使用自我對準金屬矽化物製程設計微晶矽薄膜電晶體(Self-aligned silicided μC-Si TFTs scheme)以及上層閘極堆疊式微晶矽薄膜電晶體 (Top gate staggered-type μC-Si TFTs)的特性改良。
在本論文中，我們將經由模擬來探討微晶矽薄膜電晶體，一開始會先討論使用自我對準金屬矽化鎳設計的微晶矽薄膜電晶體。我們發現與上層閘極堆疊式薄膜電晶體比較，自我對準金屬矽化鎳設計的元件擁有較大的導通電流，這是因為在閘極施加偏壓時，源極端可以造成較大的能帶彎曲，使得較多的載子可以形成穿隧電流，同時源汲極電極較靠近通道其寄生串聯電阻較小。接著改變不同的金屬矽化物厚度，研究厚度對元件特性的影響。
接著我們研究對上層閘極堆疊式薄膜電晶體不同的通道層厚度對元件特性造成的影響，結果發現當通道層厚度與源汲極電極厚度相同時，其導通電流大於其他通道層厚度。最後與使用單一電極上層閘極堆疊式薄膜電晶體元件相比，使用堆疊電極可以達到較佳的nmos與pmos驅動電流。

Microcrystalline silicon thin-film-transistors (μC-Si TFTs) have been widely studied. Due to better device characteristic, and large area growth using a lower temperature process, compared to amorphous silicon thin-film-transistors, it has larger electron field mobility and lower energy band gap. Recently, it has been believed can substitute for the a-Si:H TFTs on large substrate area liquid crystal displays application status. However, μC-Si TFTs has some unavoidable problems, such as, large leakage current, non-uniform on fabrication, and worse device characteristic than polycrystalline silicon TFTs. For the improvement of device characteristic and the process simplification for μC-Si TFTs, in this thesis, μC-Si TFTs formed by using self-aligned silicided scheme and top gate staggered-type μC-Si TFTs structure have been studied, respectively.
In this thesis, μC-Si TFTs were examined by device simulation. First, the self aligned silicided scheme μC-Si TFTs are discussed. As compared to the previous top-gate staggered structure, the self-aligned silicided scheme leads to larger bending of energy band near the source region, which facilitates causing more carriers tunneling. In addition, for the top-gate staggered structure, since the source/drain electrode is spaced from the surface channel layer, the parasitic series resistance between the electrode and surface channel layer is considerably caused. As a result, the self-aligned silicided scheme can cause a larger conduction current than the top-gate staggered structure. Following, the silicide thickness of self aligned silicided scheme is changed, to study its influence to device characteristic.
Second, top gate staggered type μC-Si TFTs with difference channel layer thicknesses are discussed. It is found that, for a given electrode thickness, a proper channel layer thickness should be chosen to achieve better device characteristic. Finally, as compared with single electrode metal, the stacked electrode can achieve a better trade-off between nmos and pmos driving current.

Abstract(chinese).................................I
Abstract..........................................III
Acknowledgement(Chinese)..........................V
Contents..........................................VI
Figure Captions...................................VIII
Chapter1 Introduction.............................1
1-1 Application of thin-film TFTs.................1
1-2 Background....................................1
1-3 Electrical Characteristics of μc-Si TFTs......3
1-4 Motivation....................................4
1-5 Thesis organization...........................5
Chapter2 Device scheme............................6
2-1 Top gate staggered-type μC-Si TFTs............6
2-2 Self-aligned nickel silicided source/drain μC-Si TFTs.............8
Chapter3 Results and Discussion.......................................14
3-1 Electrical characteristics of the self-aligned silicided source/drain microcrystalline silicon TFTs.........................................14
3-1-1 Self-aligned silicided source/drain microcrystalline silicon TFTs by using nickel silicide.................................................14
3-1-2 Influence of silicide thickness for self-aligned silicided source/drain microcrystalline silicon TFTs.........................................16
3-1-3 Self-aligned silicided source/drain microcrystalline silicon TFTs by using palladium silicide..............................................18
3-2 The influence of channel layer thickness and stack electrode for top gate staggered-type microcrystalline silicon TFTs..........................37
3-2-1 The influence of channel layer thickness for top gate staggered-type microcrystalline silicon TFTs.........................................37
3-2-2 The influence of stack electrode for top gate staggered-type microcrystalline silicon TFTs.........................................40
Chapter4 Conclusion...................................................63
Reference.............................................................65
Vita.............................................................68

[1].F. Hayashi, H. Ohkubo, T. Takahashi, S. Horiba, K. Noda, T. Uchida, T. Shimizu, N. Sugawara, and S. Kumashiro, "Highly stable SRAM memory cell with top-gated P--N drain poly-Si TFTs for 1.5V operation," IEDM Tech. Dig., pp. 283-286, (1996).
[2].H. Ohshima, and S. Morozumi, "Future trends for TFT integrated circuits on glass substrates," IEDM Tech. Dig., pp. 157-160, (1989).
[3].M. H. Juang, and Y. M. Chiu, "High-performance polycrystalline-Si thin film transistors formed by using large-angle-tilt implanted drains," Semiconductor Science and Tech., Vol. 20, pp. 1223-1225 (2005).
[4].H. Kuriyama, T. Okada, M. Ashida, O. Sakamoto, K. Yuzuriha, K. Tsutsumi, T. Nishimura, K. Anami, Y. Kohno, and H. Miyoshi, "An asymmetric memory cell using a C-TFT for ULSI SRAMs," Symp. On VLSI Tech., pp. 38-39 (1992).
[5].T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, and T. Nagano, "Advanced TFT SRAM cell technology using a phase-shift lithography," IEEE Trans. on Electron Devices, Vol. 42, pp. 1305-1313 (1995).
[6].Sato, Y. Momiyama, Y. Nara, T. Sugii, Y. Arimoto, and T. Ito, "A 0.5-μm EEPROM cell using poly-Si TFT technology," IEEE Trans. on Electron Devices, Vol. 40, pp. 2126 (1993).
[7].N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, "The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-si TFT process," IEEE Trans. on Electron Devices, Vol. 43, pp.1930 (1996).
[8].S. D. Brotherton, "Polycrystalline silicon thin film transistors," Semiconductor Science and Tech., Vol.10, pp. 721 (1995).
[9].C. C. Tsai, Y. J. Lee, J. L. Wang, K. F. Wei, I. C. Lee, C. C. Chen, and H. C. Cheng, "High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization," Solid-State Electronics, Vol. 52, pp. 365 (2008).
[10].M. H. Juang, C. W. Huang, C. W. Chang, D. C. Shye, C. C. Hwang, J. L. Wang, and S. L. Jang, "The formation of polycrystalline-Si thin-film transistors by using large-angle-tilt-implantation of dopant through gate sidewall spacer," Solid-State Electronics, Vol. 53, pp.1036 (2009).
[11].I. C. Cheng, S. Allen, and S. Wagner, "Evolution of nanocrystalline silicon thin film transistor channel layers," Journal of Non-Crystalline Solids, Vol.338-340, pp.720 (2004).
[12].C. H. Lee, A. Sazonov, and A. Nathan, "High-mobility nanocrystalline silicon thin-film transistors fabricated by plasma-enhanced chemical vapor deposition," Applied Physics Letters, Vol.86, 222106 (2005).
[13].K. Y. Chan, E. Bunte, H. Stiebig, and D. Knipp, "Influence of contact effect on the performance of microcrystalline silicon thin-film transistors," Applied Physics Letters, Vol.89, 203509 (2006).
[14].K. Y. Chan, J. Kirchhoff, A. Gordijn, D. Knipp, and H. Stiebig, "Ambipolar microcrystalline silicon thin-film transistors," Thin Solid Films, Vol.517, pp.6383 (2009).
[15].K. Y. Chan, D. Knipp, J. Kirchhoff, A. Gordijn, and H. Stiebig, "Ambipolar microcrystalline silicon transistors and inverters," Solid-State Electronics, Vol.53, 635-639 (2009).
[16].O. Vetterl, F. Finger, R. Carius, P. Hapke, L. Houben, O. Kluth, A. Lambertz, A. Muck, B. Rech, and H. Wagner, "Intrinsic microcrystalline silicon: A new material for photovoltaics," Solar Energy Materials and Solar Cells, Vol.62, pp.97 (2000).
[17].R. Platz, and S. Wagner, "Intrinsic microcrystalline silicon by plasma-enhanced chemical vapor deposition from dichlorosilane," Applied Physics Letters, Vol.73, pp.1236 (1998).
[18].T. Kamins, Polycrystalline silicon for integrated circuits and displays, second edition.
[19].S. Ferrero, P. Mandracci, G. Cicero, F. Giorgis, C. F. Pirri, and G. Barucca, "Large area microcrystalline silicon films grown by ECR-CVD," Thin Solid Films, Vol. 383, pp.181 (2001).
[20].F. Finger, S. Klein, R. Carius, T. Dylla, O. Vetterl, and A. L. Baia Neto, "Microcrystalline silicon prepared with hot-wire CVD," Journal of Materials Science: Materials in Electronics, Vol. 14, pp.621 (2003).