臺灣博碩士論文加值系統

本論文提出一個自動化設計運算放大器的流程，並提供四種常用架構的運算放大器：伸縮(telescopic)、摺疊疊接 (folded cascade)、電流鏡(current mirror)、雙級 (two stage)。整套流程已經以C++實現並連結HSPICE輔助設計。使用者只需要輸入需求的規格及選擇運算放大器的架構，便可以得到符合規格的電路。放大器是類比電路中基本的元件，並且在很多電路中都被廣泛應用。自動化設計運算放大器的流程將加速類比電路的設計，降低類比電路的設計時間。
隨著CMOS製程技術的下降，由於超大型積體電路(VLSI)複雜度的增加，以及SoC (System on Chip)的發展，驗證電路設計的正確性變的比以前困難，模擬時間也隨之上升。為了減少模擬的時間，提供所需的放大器的同時，也提供了一個運算放大器的行為模型，可以在行為模式模擬電路，驗證整體系統的正確性。

An automation flow of OP Amplifer design is proposed in this thesis. Four common OP Amplifers topologies: telescopic、folded cascade、current mirror and two stage are supported in this flow. It has been implemented by C++ program and HSPICE. Given the required specification and target topology, the tool will offer the circuit with detailed sizes that meets the required specification in the choosed topology. OP Amplifers are the fundamental components in analog circuits that have been used in many kinds of circuits extensively. An automation flow of OP Amplifer design can greatly decrease the design time of the analog circuit.
As CMOS process technology scales, the increasing complexity of VLSI systems also increase the simulation time and verification efforts. In order to reduce the simulation time, the behavioral models of the generated OP circuits are provided simultaneously, which can be used to verify the behavior of the entire system at behavioral level to reduce the system simulation time.

摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VII
表目錄 IX
第1章 序論 1
1.1 背景 1
1.2 研究動機 3
1.3 論文組織 5
第2章 背景知識 6
2.1 序論 6
2.2 Telescopic OPA 7
2.2.1運算放大器主體架構 7
2.2.2 共模回授電路 8
2.2.3 偏壓電路 9
2.2.4 Telescopic整體電路架構 10
2.3 Folded OPA 11
2.3.1運算放大器主體架構 11
2.3.2 共模回授電路 12
2.3.3偏壓電路 13
2.3.4 Folded整體電路架構 14
2.4 Current Mirror OPA 15
2.4.1運算放大器主體架構 15
2.4.2 偏壓電路 16
2.4.3 Current Mirror整體電路架構 17
2.5 Two Stage OPA 18
2.5.1運算放大器主體架構 18
2.5.2 補償電路 19
2.5.3 偏壓電路 20
2.5.4 Two Stage整體電路架構 21
第3章 自動化設計流程 22
3.1 序論 22
3.2 從HSPICE得到電路的資訊與建立表格 24
3.3 根據規格初步估算 25
3.3.1 Telescopic OPA 25
3.3.3 Folded OPA 36
3.3.5 Current Mirror OPA 45
3.3.7 Two Stage OPA 51
3.4 套入先前假設參數的實際值 57
3.5 降低過度設計的規格以減少面積 58
3.5.1 檢查是否有過度設計的規格 59
3.5.2 選擇欲調整的電晶體 60
3.5.3 降低電晶體的面積 61
3.5.4 檢查是否符合規格 62
3.5.5 恢復電晶體的面積 62
第4章 行為模型 63
4.1 序論 63
4.2 可套入的電路特性 64
4.3 行為模型的建立 65
4.4 用行為模型量測的結果 66
第5章 實驗結果 68
5.1 序論 68
5.2 工具功能說明 68
5.3 Telescopic OPA 69
5.4 Folded OPA 71
5.5 Current Mirror OPA 72
5.6 Two Stage OPA 73
第6章 結論與未來研究方向 75
參考文獻 76

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