臺灣博碩士論文加值系統

消費性電子產品由於市場競爭激烈，使得設計者必須在很短的時間內完成產品的開發，以取得市場的先機。因此，一個有效率系統發展方法對此類產品的開發極為重要。軟硬體協同設計經由系統功能的分割、排程以及通訊介面的規劃，使得系統中的軟硬體模組能夠被同步設計、模擬與驗證，達到縮短產品開發時間、降低成本以及有效運用人力資源的目標。
多數的消費性電子產品具有多媒體的功能，而由於僅能使用有限容量的儲存裝置，所以影音資料必須經過壓縮處理。JPEG是一種影像壓縮技術，對於自然影像有高壓縮比與低失真的處理效果，因此有眾多消費性電子產品在靜態影像處理上，選擇JPEG為首要支援標的。本論文以JPEG為例，以軟硬體協同設計的方式建立JPEG解碼器。由分析得知，逆離散餘弦轉換為解碼過程中佔總運算時間最大比重的步驟，因此我們對解碼過程進行軟硬體功能分割，其中熵解碼與反量化步驟以軟體實現，而逆離散餘弦轉換與數值正規化以FPGA實作。原先循序的解碼過程經由軟硬體功能分割後轉換成為軟硬體平行處理。論文最後完成一嵌入式JPEG解碼器原型，展現出協同設計在系統開發上的可行性。

The development process for consumer-electronics products is often characterized by relatively short time-to-market, because of intensive competition. An efficient development process is, therefore, crucial to the successful introduction of such a product into the marketplace. Hardware/software codesign is a development methodology which involves proper partitioning and scheduling of the hardware and software parts within a system. Through well-defined communication interfaces, the hardware and software modules can be designed, simulated, and verified in parallel and in a coordinated fashion. The results are shorter development time, lower system cost, and more efficient management of manpower.
The capability to handle multimedia is a common feature of many consumer- electronics products. Due to limited storage capacity, image and sound are normally compressed in these devices. For the storage and display of still images, JPEG standard is widely supported due to its high compression ratio and relatively low distortion. This thesis describes our effort in building an embedded JPEG decoder by using a hardware/software codesign approach. In partitioning the JPEG decoding process, the inverse discrete cosine transform (IDCT) is found to be the most time-consuming computation and, therefore, together with the normalization operation, are implemented in hardware using an FPGA. On the other hand, the entropy decoding and dequantization are realized in software such that their execution overlaps the hardware operations in a pipelined fashion. The finished prototype for the embedded JPEG decoder successfully demonstrates the effectiveness of the underlying development methodology.

目 錄
圖目錄iii
表目錄v
第一章 緒論1
第二章 相關背景知識3
2-1 JPEG標準3
2-1-1 JPEG的色彩模型4
2-1-2 準位偏移4
2-1-3 離散餘弦轉換5
2-1-4 量化6
2-1-5 DPCM編碼7
2-1-6 Zigzag排序法則7
2-1-7 RLE編碼8
2-1-8 霍夫曼編碼8
2-2離散餘弦轉換快速演算法9
2-3嵌入式系統15
2-4軟硬體協同設計16
第三章 系統設計與實作20
3-1 發展環境20
3-2 系統分析21
3-3 軟硬體功能劃分25
3-4 FPGA硬體設計29
3-4-1 IDCT模組29
3-4-2 Controller模組32
第四章 系統驗證與效能測試34
4-1 系統時序34
4-2 FPGA佈局分析38
4-3 FPGA驗證39
4-4 效能測試40
4-5 系統效能評估44
第五章 結論與未來發展45
參考文獻46
附錄A48
附錄B50
附錄C52
圖目錄
圖2-1 JPEG編碼/解碼流程3
圖2-2 JPEG量化表6
圖2-3 Zigzag排序方式7
圖2-4 熵編碼器8
圖2-5 即時性嵌入式系統概圖16
圖2-6 軟硬體協同設計流程17
圖3-1 JPEG解碼器軟體開發流程21
圖3-2 JPEG解碼器之軟體設計處理流程22
圖3-3 嵌入式JPEG解碼器之工作時程規劃25
圖3-4 嵌入式JPEG解碼器之功能區塊對應26
圖3-5 FPGA內部之功能區塊規劃27
圖3-6 IDMA協定28
圖3-7 IDCT top level實體表示29
圖3-8 IDCT模組結構30
圖3-9 aan16m2模組設計30
圖3-10 aan16m2模組設計31
圖3-11 aan16m3模組設計31
圖3-12資料輸出入控制流程32
圖3-13資料流向控制程序33
圖4-1 IDCT phase 0 時序圖35
圖4-2 IDCT phase 1 時序圖36
圖4-3 Top Entity 時序圖37
圖4-4 FPGA Express合成結果38
圖4-5 IDCT phase 0實體驗證39
圖4-6 IDCT phase 1實體驗證39
圖4-7 重建與原始lena影像之比較41
圖4-8 重建與原始gallop影像之比較42
圖4-9 重建與原始child影像之比較43
圖A-1 栓鎖位址時序48
圖A-2 讀取資料時序49
圖A-3 寫入資料時序49
表目錄
表2-1 IDCT所使用運算子種類與數目分析14
表4-1 Max+PlusII數據分析38
表4-2 SNR效能測試數據40
表A-1 IDMA埠訊號腳位48

[1]William B. Pennebaker, Joan L. Mitchell, JPEG Still Image Data Compression Standard, Van Nostrand Reinhold, 1993.
[2]Henry Chang,Larry Cooke,Merril Hunt,Grant Martin,Andrew McNelly,Lee Todd,Surviving the SOC Revolution, Kluwer Academic Publishers, 1999.
[3]Michael Keating,Pierre Bricaud, Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition, Kluwer Academic Publishers, 1999
[4]John Miano, Compressed Image File Formats : JPEG,PNG,GIF,XBM,BMP, Addison-Wesley, 1999.
[5]K. R. Rao, P. Yip, Discrete Cosine Transform : Algorithms,Advantages,and Applications, Academic Press, 1990.
[6]John Watkinson, MPEG-2, Focal Press, 1999.
[7]Peter Symes, Video Compression, McGraw-Hill, 1998.
[8]D. A. Huffman, "A Method for The Construction of Minimum Redundancy Codes," In Pro. IRE, 40, 10981101, 1952.
[9]Y. Arai, T. Agui, and M. Nakajima. A Fast DCT-SQ Scheme for Images. Trans. of the IEICE. E 71(11):1095, Nov. 1988.
[10]Ralf Niemann, Hardware/Software Co-Design for Data Flow Dominated Embedded Systems, Kluwer Academic Publishers, 1998.
[11]G. Goossens, J. Van Praet, D. Lanneer, W. Geurts, A. Kifli, C. Liem, P. G. Paulin, "Embedded Software in Real-Time Signal Processing Systems: Design Technologies," In Proceedings of The IEEE : Special Issue on Hardware/Software Co-design, March 1997.
[12]P. G. Paulin, C. Liem,M. Cornero, F. Naccabal, G. Goossens, "Embedded Software in Real-Time Signal Processing Systems : Applications and Architecture Trends," In Proceedings of The IEEE : Special Issue on Hardware/Software Co-design, March 1997.
[13]G.De Micheli and R. K. Gupta, "Hardware/Software Co-Design," In Proceedings of The IEEE : Special Issue on Hardware/Software Co-design, March 1997.
[14]Michael John Sebastian Smith, Application-Specific Integrated Circuits, Addision-Wesley, 1998.
[15]Amos R. Omondi, The Microarchitecture of Pipelined and Superscalar Computers, Kluwer Academic Publishers, 1999.
[16]M. Morris Mano, Computer Engineering : Hardware Design, Prentice Hall International, 1988.