臺灣博碩士論文加值系統

本論文介紹了適用於有線電視接收器類比前端的設計。此類比前端具有雙回授回路，並利用一個量化器調節自動增益控制的回路頻寬，這樣的設計可以同時達到快速收斂及穩定的穩態響應。為了減少製程變異對電路特性的影響，我們採用數位電路製作自動增益控制的回授電路。另外整個類比前端也包含了可變增益放大器，帶通濾波器，和增益級。整顆晶片是利用0.6um N-well single poly triple metal CMOS製程製作，模擬結果顯示該晶片可以提供25dB動態增益範圍，3.8KHz初始回路頻寬，240Hz穩態回路頻寬。通帶的頻率為1.2MHz到7MHz，在600KHz和14MHz各提供了19dB和36dB的訊號衰減。類比電路功率消耗為70mW，數位電路則為24mW。

In this thesis, the design and implementation of analog front end for digital cable modem are introduced. A quantizer is utilized in the automatic gain control (AGC) to regulate its loop bandwidth, which can accomplish fast acquisition and low gain fluctuation simultaneously. Meanwhile, to achieve robustness against various variations and good programmability, mixed mode circuit architecture is adopted. Except for the inevitable analog circuits such as variable gain amplifier (VGA), receive bandpass filter (Rx BPF) and gain/buffer (G/B), the rest parts are realized in digital form. Careful design optimization and parameter assignment are performed before layout. Implemented in 0.6um N-well single poly triple metal (SPTM) digital CMOS technology, the analog front end provides 25dB dynamic range, 240Hz acquisition loop bandwidth and 3.8KHz steady-state loop bandwidth for both 64QAM and 8VSB signals. The passband ripple from 1.2MHz to 7MHz is less than 1dB, and the out-of-band attenuation at 600KHz and 7MHz are 19dB and 36dB, respectively. The analog forward path consumes 70mW under 3.3V supply voltage while the digital feedback path draws 24mW from 5V supply voltage.

Contents
1.Introduction ................................................................................................ 1
1.1Intorduction ........................................................................................ 1
1.1.1Local Access for Telephone Companies ............................ 1
1.1.2Local Access for Cable TV Companies ............................. 2
1.2Thesis Organization ............................................................................ 2
2.Automatic Gain Control ............................................................................. 4
2.1Introduction to Cable Modem Tranceiver Architecture ..................... 4
2.1.1Transmitter ......................................................................... 4
2.1.2Receiver .............................................................................. 5
2.2Automatic Gain Control ..................................................................... 6
2.3Dual-Loop Mixed-Mode AGC ........................................................... 9
2.4AGC Linear Model ........................................................................... 10
2.4.1Macro Behavior Modeling ............................................... 11
2.4.2Mathematical Analysis ..................................................... 13
2.5AGC System Design Model ............................................................. 15
2.6Design Methodology ........................................................................ 16
3.Analog Forward Path Circuit Designs ..................................................... 19
3.1Variable Gain Amplifier ................................................................... 19
3.2Bandpass Filter ................................................................................. 25
3.3Gain/Buffer ....................................................................................... 30
3.4Complete Forward Path .................................................................... 32
4.Digital Feedback Path Circuit Designs .................................................... 35
4.1Circuit Designs ................................................................................. 35
4.1.1Magnitude Detector .......................................................... 35
4.1.2Loop Filter ........................................................................ 36
4.2Closed Loop Simulation Results ...................................................... 37
4.2.1Floating Point Simulation ................................................. 37
4.2.2Bit Level Simulation ........................................................ 39
4.2.3Verilog Simulation Results ............................................... 40
5.VLSI Implementation ............................................................................... 42
5.1Layout Considerations ...................................................................... 42
5.2Post-Layout Simulation Results ....................................................... 42
5.2.1Macro ............................................................................... 42
5.2.2Open Loop ........................................................................ 45
6.Conclusions .............................................................................................. 51
Appendix ATest Strategies ........................................................................... 52
Appendix BPin Assignment ........................................................................ 53

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