臺灣博碩士論文加值系統

在本文中，我們將會介紹三個以65-nm CMOS 製程製作的有線背板電路系統，包括10 Gb/s 的決策回饋等化器、20 Gb/s 的收發器以及40 Gb/s 的收發器。
在10 Gb/s 的決策回饋等化器中，他包含了一個類比等化器和一個有可適應性迴路的決策回饋等化器。這個晶片在以211−1 PRBS 的編碼下，可以走FR4 這種板材的傳輸線80 公分，並且達到位元誤碼率小於10−12。此外，這個電路在1 伏特的操作電壓下，消耗31 毫瓦，晶片面積則為0.1 平方公厘。
在20 Gb/s 的收發器中，我們在傳輸端製作了27-1 PRBS 產生器、注入式鎖相迴路和前饋等化器，在接收端則有一可適應性的類比等化器以及資料時脈回復電路。這個系統可以傳輸在60 公分的FR4 板材下達到位元誤碼率小於10−13，並且在傳輸端操作電壓1.2 伏特的情況下消耗310 毫瓦、接收端操作電壓1.3 伏特的情況下消耗190 毫瓦，而晶片面積在傳輸端與接收端分別為0.27 平方公厘和0.32平方公厘。
在40 Gb/s 的收發器中，我們在傳輸與接收端都使用延遲線架構的前饋等化器，其中在接收端的前饋等化器還有一個可適應性迴路。我們把這組晶片安置在羅捷士RO 4003 這種板材上，在27−1 PRBS 的編碼下可以傳遞20 公分。傳輸端在操作電壓為1.2 伏特的情況下消耗135 毫瓦、接收端在操作電壓為1.6 伏特的情況下消耗322 毫瓦，而晶片面積在傳輸端與接收端分別為0.63 平方公厘和0.66 平方公厘。

In this thesis, three wireline backplane circuit systems will be demonstrated, including a 10 Gb/s Decision Feedback Equalizer (DFE), a 20 Gb/s Transceiver Chip-set, and a 40 Gb/s Transceiver Chip-set. They are all implemented in 65-nm CMOS Technology.
First of all, in 10 Gb/s Decision Feedback Equalizer, it consists of an analog equalizer and a decision feedback equalizer with an adaptation loop. This circuit achieves BER < 10−12 for 211−1 PRBS in 80 cm FR4 channel, and consumes 31 mW with 1 V supply. Besides, the chip area is less than 0.1 mm2.
In 20 Gb/s Transceiver Chip-set, a 27−1 PRBS generator, an injection-locked PLL, and a 3-Tap feed-forward equalizer (FFE) are implemented in transmitter side. An adaptive analog equalizer and CDR are implemented in receiver side. This system achieves BER < 10−13 in a 60 cm FR4 channel, and consumes 310 mW and 190 mW with 1.2 V and 1.3 V supply in transmitter and receiver, respectively. The chip occupies 0.27 mm2 in transmitter and 0.32 mm2 in receiver.
Finally, in 40 Gb/s Transceiver Chip-set, we propose a delay-line-based feed-forward equalizer in both transmitter and receiver, and an adaptation loop is implemented in receiver. We mount transmitter and receiver chip on Rogers RO 4003 board with 20 cm transmission line, and the chip-set can achieve BER < 10−12 for 27−1 PRBS. This chip-set occupies 0.63 mm2 in transmitter and 0.66 mm2 in receiver, and consumes 135 mW with 1.2 V supply and 322 mW with 1.6 V in transmitter and receiver, respectively.

摘要------------------------------------------------------------------------------------------------ I
ABSTRACT-------------------------------------------------------------------------------------- II
CONTENTS------------------------------------------------------------------------------------- IV
LIST OF FIGURES ---------------------------------------------------------------------------- VI
LIST OF TABLES------------------------------------------------------------------------------- X
Chapter 1 Introduction1 ---------------------------------------------------------------------1
1.1 Motivation -------------------------------------------------------------------------------1
1.2 Thesis Organization---------------------------------------------------------------------4
Chapter 2 A 10 Gb/s Decision Feedback Equalizer ------------------------------------5
2.1 Introduction of Decision Feedback Equalizer (DFE)-------------------------------5
2.2 System Architecture --------------------------------------------------------------------6
2.3 2.2.1 Analog Equalizer---------------------------------------------------------------7
2.3 2.2.2 Summing Amplifier------------------------------------------------------------8
2.3 2.2.3 Delay Cell-----------------------------------------------------------------------9
2.3 2.2.4 Sign-Sign Block Least Mean Square (SS-BLMS) Algorithm ---------- 11
2.3 2.2.5 SS-BLMS Core Operation -------------------------------------------------- 12
2.3 Measurement Results ----------------------------------------------------------------- 14
2.4 Performance Summary --------------------------------------------------------------- 15
Chapter 3 A 20 Gb/s Transceiver Chip-set --------------------------------------------- 17
3.1 Transmitter Architecture ------------------------------------------------------------- 17
3.1 3.1.1 10 GHz Injection-Locked PLL --------------------------------------------- 18
3.1 3.1.2 Half-Rate 27−1 PRBS Generator------------------------------------------- 19
3.1 3.1.3 Feed-Forward Equalizer (FFE)--------------------------------------------- 22
3.2 Receiver Architecture----------------------------------------------------------------- 24
3.2 3.2.1 Adaptive Analog Equalizer ------------------------------------------------- 24
3.2 3.2.2 CDR---------------------------------------------------------------------------- 25
3.3 Measurement Results ----------------------------------------------------------------- 28
3.3 3.3.1 Transmitter Measurement --------------------------------------------------- 29
3.3 3.3.2 CDR Measurement----------------------------------------------------------- 35
3.3 3.3.3 Transceiver Measurement--------------------------------------------------- 38
3.4 Performance Summary --------------------------------------------------------------- 44
Chapter 4 A 40 Gb/s Transceiver Chip-set --------------------------------------------- 46
4.1 Transmitter Architecture ------------------------------------------------------------- 46
3.3 4.1.1 5-Tap Feed-Forward Equalizer --------------------------------------------- 47
3.3 4.1.2 Layout Topology of Feed-Forward Equalizer ---------------------------- 49
3.3 4.1.3 1-UI Delay Generator ------------------------------------------------------- 50
4.2 Receiver Architecture----------------------------------------------------------------- 52
4.3 Measurement Results ----------------------------------------------------------------- 54
4.3 4.3.1 Transmitter Measurement --------------------------------------------------- 54
4.3 4.3.2 Transceiver Measurement--------------------------------------------------- 59
4.4 Performance Summary --------------------------------------------------------------- 62
Chapter 5 Conclusion--------------------------------------------------------------------- 64
Bibliography------------------------------------------------------------------------------------ 67

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