臺灣博碩士論文加值系統

本論文提出一個低成本、高符元率適用於符合HIPERLAN規格的高速區域網路的等化器晶片。雖然HIPERLAN的通道是一個緩時變多通道模式，但由於高達20Mbps的資料傳輸，使得其訊號間雜訊干擾 (ISI, Inter-symbol Interference)現象非常嚴重，因此選擇了適應性決策回授等化器(ADFE, Adaptive Decision Feedback Equalizer)來解決這個問題。
我們採用序向架構來降低ADFE的硬體成本，然而此架構所需的工作頻率將比平行架構高出十倍，為了符合系統規格，此晶片需要設計高速的乘法器以及加法器，同時我們鉗入一個全數位鎖相迴路(ADPLL, All Digital Phase-Locked Loop)來推動高頻的時脈。

A low-cost high-symbol-rate equalizer for the receiver of a high-speed local area network that meets the ETSI HIPERLAN standard is proposed in this thesis. Although the HIPERLAN is a Slowly Time-varying Multipath Fading Channel system, the ISI (Inter-symbol Interference) will be very severe when the data rate up to 20Mbps. In this thesis, we select ADFE (Adaptive Decision Feedback Equalizer) to overcome the ISI problem.
We adopt the sequential architecture to reduce the ADFE hardware cost. However, a ten times operation clock frequency comparing to the parallel ADFE is applied to the whole system. Therefore the high-speed multiplier and adder are necessary for this chip. In order to solve the problem of clock skew we also embed an ADPLL (All Digital Phase-Locked Loop) to boost the operation clock frequency.

ABSTRACT
CHAPTER 1INTERODUCTION
1.1 Motivations
1.2 Thesis Organization
CHAPTER 2THE HIPERLAN SYSTEM
2.1 Introduction
2.2 The Architecture of Transmitter
2.3 The Channel Model
2.4 The Architecture of Receiver
2.5 The Consideration of Equalizer Selection
2.6 The C-code Simulation Result
CHAPTER 3THE ANALYSIS and DESIGN OF THE ADFE ARCHITECTURE
3.1 Introduction
3.2 The Comparison of Parallel and Sequential Architecture
3.3 The Building Blocks of the Sequential ADFE
3.3.1 Feedforward Filter
3.3.2 Feedback Filter
3.3.3 Coefficient Update Block
3.3.4 Detector
3.3.5 ADPLL
3.4 The RTL Simulation Result
3.5 Summary
CHAPTER 4THE DESIGN FLOW and CHIP IMPLEMENTATION of ADFE
4.1 Overview
4.2 Design Flow
4.3 The Data Path of Each Block
4.3.1 Feedforward Filter
4.3.2 Feedback Filter
4.3.3 Coefficient Update Block
4.3.3.1 Feedforward part
4.3.3.2 Feedback part
4.3.4 Detector
4.3.5 Timing Controller
4.3.6 ADPLL
4.4 The Detail Circuit Design of Critical Block
4.4.1 Multiplier
4.4.2 Adder
4.5 Post-Layout Simulation Result
4.6 Chip Summary
CHAPTER 5CONCLUSIONS
REFERENCE

[1] B.Bourin, "HIPERLAN-Markets and Applications Standardization issues," WCN, 1994.
[2] Y. Sun & A. Nix, "A Simulation of Combined Equalization and Diversity Combining and its impact on the HIPERLAN Standard," IEE, 1995.
[3] G.A.Halls, "HIPERLAN: The High Performance Radio Local Area Network Standard," Electronics & Communication Engineering Journal, Dec 1994.
[4] Perry, R. & Bull, D.R. & Nix, A. "A High Throughput Adaptive DFE for HIPERLAN," Circuits and Systems, ISCAS '96, 1996.
[5] Perry, R. & Bull, D.R. & Nix, A. "An Adaptive DFE for High Data Rate Applications," Vehicular Technology Conference, 1996.
[6] H. C. Reve, R. B. Ward, C. J. Lin, G. D. Martin, "An 11-Tap 0.9μ CMOS Digital Transversal Equalizer For Digital Radio," IEEE, 1989.
[7] Erik De Man, Tobias G. Noll, Michael Schulz, Richard Schmidmaier, Matthias Schobinger, "Architecture and Circuit Design of a 6-GOPS Signal Processor for QAM Demodulator Applications," IEEE JSSC, Mar 1995.
[8] Kazuya Yamanaka, Sumitaka Takeuchi, Shuji Murakami, "A Multilevel QAM Demodulator VLSI with Wideband Carrier Recovery and Dual Equalizing Mode," IEEE JSSC, Jul 1997.
[9] Issam S. Abu-Khater, M. I. Elmasry, "Circuit Techniques for CMOS Low-Power High-Performance Multipliers," IEEE JSSC, Oct 1996.
[10] Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu, " A 3.8-ns CMOS 16*16-b Multiplier Using Complementary Pass-Transistor Logic," IEEE JSSC, Apr 1990.
[11] Sheng Duo, "An All Digital Phase Locked-Loop (ADPLL) with Fast Lock-In Time - Analysis, Implementation and Application," Master Thesis, National Chung Cheng University, 1999.
[12] Sun, Y. and Nix, A. and McGeehan, J.P. "Suitable Codes Design for Frequency Offset Correction and Channel Matched Filter in HIPERLAN," 1996 5th IEEE International Conference
[13] Sun, Y. and Nix, A. and McGeehan, J.P. "HIPERLAN Performance Analysis with Dual Antenna Diversity and Decision Feedback Equalizer," Vehicular Technology Conference, 1996.
[14] K. Pahlavan and A.H.Levesque, "Wireless Information Networks," New York:John Wiely & Sons, 1995.
[15] C.A. Belfiore and J. H. Park, Jr., "Decision-Feedback equalization," Proc. IEEE, vol. 67, pp. 1143-1156, August 1979.
[16] S. U. H. Qureshi, "Adaptive equalization," Proc. IEEE, vol. 73, pp. 1349-1387, 1985.
[17] G. D. Forney, "Maximum likelihood sequence estimation of digital sequences in the presence of intersymbol interference, " IEEE Trans. Inform. Theory, vol. IT-18, no. 3, pp. 363-378,1972.
[18] Perry, R.; Bull, D.R.; Nix, A. " An Adaptive DFE for High Data rate Application," Vehicular Technology Conference, 1996.
[19] Caesar S. H. Wong, Jacques C. Rudell, Gregory T. Uehara, Paul R. Gray, "A 50MHz Eight-Tap Adaptive Equalizer for Partial-Response Channels," IEEE JSSC, Mar 1995.
[20] Fang Lu, Henry Samueli," A 60-MBb, 480-Mb/s, 256-QAM Decision-Feedback Equalizer in 1.2-μm CMOS," IEEE JSSC, Mar 1993.
[21] Henry Samueli, Babak Daneshrad, Robindra B. Joshi, Bennett C. Wong, Henry T. Nicholas, " A 64-Tap CMOS Echo Canceller/Decision Feedback Equalizer for 2B1Q HDSL Transceivers," IEEE Journal on Selected Areas in Communications," Aug 1991.
[22] Henry Samueli, Robindra B. Joshi, " A 100MHz, 5Mbaud QAM Decision-Feedback Equalizer for Digital Television Applicatoins" IEEE International Solid-State Circuits Conference, 1994.