臺灣博碩士論文加值系統

本論文提出一個操作電壓低於0.7伏特應用於無線區域網路的5-GHz低功率直接降頻式射頻前端接收器。此射頻接收器包含的電路有低雜訊放大器，可補償直流偏差的降頻器和正交壓控振盪器，透過國家晶片系統設計中心委託台灣積體電路製造股份有限公司以0.18微米互補式金氧半導體的製程製造。整個射頻接收器已經被完整地設計、製造與量測完成。
量測結果顯示，此射頻接收器可在低於0.7伏特的操作電壓下正常運作，但由於對寄生效應的疏忽，量測得到的效能不如預期。其中，射頻接收器的轉換增益為12.6 dB，雜訊指數為24 dB，1 dB增益壓縮點為-24 dBm，此外，當輸入一個頻率與正交壓控振盪器的頻率相同且強度為-50 dBm的訊號至接收器的輸入端時，自身混波後產生的直流偏差小於3毫伏。此射頻接收器的消耗功率為8.14毫瓦，晶片面積為4.4 mm2。經過分析因寄生效應而產生頻率偏移的問題之後，修正過的射頻接收器即可符合IEEE 802.11a的規格。

A sub-0.7V 5-GHz direct-conversion receiver for low-power and wireless applications is proposed in this thesis. The receiver composed of a low-noise amplifier, a set of I/Q downconverters with a DC compensation circuit, and a quadrature voltage-controlled oscillator is realized in a 0.18-�慆 CMOS technology supported by Taiwan Semiconductor Manufacturing Company via Chip Implementation Center. The proposed receiver is completely designed, fabricated and tested.
Measured results exhibit that the receiver can operate well under supply voltages of 0.65 V and 0.7 V even though it doesn’t achieve adequate performance due to an oversight of parasitic effects. The receiver performs a conversion gain of 12.6 dB, a noise figure of 24 dB, a 1-dB compression point of -24 dBm, and a DC offset of less than 3 mV with an injected input power of -50 dBm, while draining 8.14 mW and covering 4.4 mm2. The problem of frequency shift in measurement is discussed and modified, and a re-designed receiver, which is able to fit the IEEE 802.11a specification, is completed.

Chinese Abstract i
English Abstract ii
Acknowledgement iii
Contents iv
Table Captions vi
Figure Captions vii

CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 A Review of CMOS RF Receiver Front-End 2
1.2.1 Receiver Architectures 3
1.2.2 Issues in Direct-Downconversion 7
1.2.3 Low-Voltage Receivers 14
1.3 Motivation 14
1.4 Thesis Organization 15

CHAPTER 2 SUB-0.7V 5-GHz DIRECT-CONVERSION
RECEIVER FRONT-END 16
2.1 IEEE 802.11a PHY Specification and Link Budget 16
2.2 Downconverter with DC-Offset Compensation 20
2.2.1 Operational Principle 20
2.2.2 DC-Offset Compensation 24
2.2.3 Circuit Implementation 27
2.3 Folded-Cascode Low-Noise Amplifier 30
2.3.1 Design Considerations 31
2.3.2 Circuit Implementation 35
2.4 Quadrature Voltage-Controlled Oscillator 37
2.5 Receiver Realization 39
2.6 Simulation Results 42

CHAPTER 3 EXPERIMENTAL RESULTS 53
3.1 Layout Description 53
3.2 Measurement Considerations and Setup 54
3.3 Experimental Results 60
3.4 Discussions and Comparisons 69

CHAPTER 4 CONCLUSIONS AND FUTURE WORKS 80
4.1 Conclusions 80
4.2 Future Works 80

REFERENCES 82

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