臺灣博碩士論文加值系統

隨著電路複雜度越來越高，在超大積體電路測試過程中，往往最終測試資料會是一個龐大的資料量，而如何將處理這龐大的資料量，在VLSI Testing領域中屬熱門探討的研究議題之一。
本論文是基於以固定區塊長度樣式為基礎，提出一個能達到更好測試資料壓縮率的方法，本論文所提之方法是以可變區塊長度搭配可變長度編碼的方式，以達到更好的測試資料壓縮率，由於嘗試的長度較多樣化且每次壓縮的選擇性多元，藉此達到增加壓縮率的目的。
我們所使用的測試資料是以ISCAS'89的六個電路s5378、s9234、s13207、s15850、s38417以及s38584。在實驗的過程中，我們儘量提升壓縮率，與原始測試資料相比，平均壓縮率可達70.42%。

The testing data compression is one of popular topics in VLSI testing field. It also is the key to solve the huge data test data. Built-in-self-test (BIST) architecture which can test the circuit itself can generate the data inside the circuit under test without any other externality, resulting the reduction of test data volume.
In this thesis, we proposed a code-based test data compression approach to achieve a better test data compression ratio by using the variable block size pattern run-length. By using benchmark ISCAS’89 circuits, experimental results show that the proposed approach can achieve test data compression ratio up to 70.42%.

目 錄
中文摘要 III
英文摘要 IV
誌 謝 V
目 錄 VI
圖目錄 VII
表目錄 VIII
第一章 簡介 1
1.1 廣播壓縮法(BROADCAST-BASED SCHEME) 1
1.2 線性壓縮法(LINEAR-DECOMPRESSION-BASED SCHEME) 1
1.3 編碼壓縮法(CODE-BASED) 2
第二章 相關研究 3
2.1FDR(FREQUENCY-DIRECTED RUN-LENGTH CODING) 3
2.2BM(BLOCK MERGING) 4
第三章 方法 6
3.1 METHOD INTRODUCTION 6
3.2 A VARIABLE BLOCK SIZE PATTERN RUN-LENGTH CODING 7
第四章 實驗結果 11
4.1實驗環境設置 11
4.2實驗數據 11
第五章 結論 14
第六章 參考文獻 15

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