臺灣博碩士論文加值系統

本論文中提出一全球定位系統專用的頻率合成器，其工作頻率在1.57GHz，為了達到低功率損耗的目的，我們將操作電壓設定在1.5伏特，且除頻器部份考慮降低電流使用量，採用較省電的整數N組態，所有電路除迴路濾波器及參考振盪器外，均製作在同一晶片上以達高整合目的，晶片製作則是採用台積電CMOS 0.25um製程。
在1.5伏特的電壓供應下，所量測到的功率損耗為14.1毫瓦。壓控振盪器消耗6.8毫瓦，除頻器消耗6.6毫瓦，充電幫浦消耗0.64毫瓦，相位/頻率比較器消耗不到1毫瓦。

In this thesis, we demonstrate a low power synthesizer for global position system (GPS) which operates at 1.57GHz. For low power consumption consideration, we set the supply voltage at 1.5V, and adopt the “Integer-N” type frequency synthesizer to save power. For high integration issue, all circuits are integrated in single chip except the loop filter and the reference oscillator. This chip is fabricated by TSMC 0.25um.
The measurement of power consumption is 14.1mW for 1.5V supply voltage. VCO consumes 6.8mW, frequency divider consumes 6.6mW, charge pump consumes 0.64mW, and phase/frequency detector consumes less than 1mW.

CONTENTS

CHINESE ABSTRACT………………………………………….……..I
ENGLISH ABSTRACT………………………………….……………II
ACKNOWLEDGMENT…………………………………..…………III
CONTENTS…………………………………………………………..IV
TABLE CAPTIONS……………………………………….………….VI
FIGURE CAPTIONS………………………………………………..VII

Chapter 1 INTRODUCTION………………………………………1
1.1 GPS background and motivation…………………1
1.2 Typical GPS frond end receiver architecture…3
1.3 Other reference works……………………………………4
1.4 Thesis organization….…………………………………6
Chapter 2 PLL THEORY AND NOISE IN PLL LOOPS……………7
2.1 Basic PLL theory……………………………………7
2.2 Noise in PLL loops…………………………………14
Chapter 3 FREQUENCY SYNTHESIZER……………………………17
3.1 VCO design…………………………………………18
3.1.1 Complementary & all-NMOS couple pair VCO……18
3.1.2 Design for low power and low phase noise……21
3.1.3 Architecture and simulation………………………23
3.2 Frequency divider design………………………28
3.3 Phase/Frequency detector design………………32
3.4 Charge pump design………………………………34
3.4.1 Single-ended & differential charge pump………34
3.4.2 Architecture and simulation………………………35
3.5 Loop filter design………………………………37
3.6 Complete loop simulation & layout……………38
Chapter 4 MEASUREMENT RESULTS………………………………40
4.1 VCO measurement……………………………………41
4.1.1 What is the problem with varactor………………42
4.2 Frequency divider measurement…………………44
4.3 PFD and charge pump measurement………………52
4.4 Discussion……………..…………………………………55
Chapter 5 CONCLUSIONS AND FUTURE PROSPECTS……………57
5.1 Conclusions…………………………………………57
5.2 Future prospects…………………………………58

REFERENCES………………………………………………………59
PUBLICATION REMARKS………………………………………….61

TABLE CAPTIONS

Table. 1 Specification summary of the first reference…4
Table. 2 Specification summary of the second reference…5
Table. 3 Specification summary of the third reference……6
Table. 4 Low-power & low-phase noise optimization summary……23
Table. 5 VCO specification summary…………………………28
Table. 6 Power consumption summary…………………………55

FIGURE CAPTIONS

Fig. 1 GPS signal……………………………………………2
Fig. 2 GPS front end receiver……………………………3
Fig. 3 Third-order PLL linear model……………………9
Fig. 4 Second-order loop filter…………………………9
Fig. 5 Transfer function of Z(s)………………………10
Fig. 6 Frequency response of |G(s)|,｜H(s)|…………11
Fig. 7 The effect of third pole in step response……13
Fig. 8 Interrelation with each pole and zero…………13
Fig. 9 The linear PLL model with noise added…………14
Fig. 10 Phase noise contributions in a PLL……………16
Fig. 11 “Integer-N” PLL architecture…………………18
Fig. 12 Two typical LC-tank oscillator structures……19
Fig. 13 Phase noise simulation results for both structures…………20
Fig. 14 Basic LC resonator tank……………………………21
Fig. 15 VCO architecture with bank sets and output buffer Vctrl…………24
Fig. 16 The measured phase noise vs. VDD and Isupply for complementary LC oscillator…………25
Fig. 17 VCO transient simulation……………………………26
Fig. 18 VCO FFT simulation……………………………………26
Fig. 19 VCO tuning range simulation………………………27
Fig. 20 VCO phase noise simulation…………………………27
Fig. 21 Frequency divider architecture……………………29
Fig. 22 Block diagram of a master-slave D-flipflop……29
Fig. 23 SCL D-latch structure………………………………30
Fig. 24 Differential Source Coupled Logic………………31
Fig. 25 VCO& Frequency divider simulation result……32
Fig. 26 Phase/Frequency detector architecture…………32
Fig. 27 fref is faster than fdiv and upp is set…………33
Fig. 28 fdiv is faster than fref and dwp is set…………34
Fig. 29 Single-ended charge pump with switch at drain …35
Fig. 30 Differential charge pump architecture……………36
Fig. 31 The simulation of Icp when upp and dwp are set…37
Fig. 32 Passive loop filter architecture…………………37
Fig. 33 Settling time simulation with fix channel………38
Fig. 34 Settling time simulation when sweeping channel…39
Fig. 35 Layout of the synthesizer………………………39
Fig. 36 Die photo………………………………………………40
Fig. 37 All measurable points of VCO…………………….42
Fig. 38 PCB of frequency divider measurement…………44
Fig. 39 Photograph of instruments ………………………45
Fig. 40 Probe pad photo ……………………………………46
Fig. 41 Probe pad diagram……………………………………47
Fig. 42 First stage sets to divide-by-2 model…………48
Fig. 43 First stage sets to divide-by-3 model…………48
Fig. 44 Only the first stage is set to divide-by-3 model………49
Fig. 45 Both of the first and the second stage are set to divide-by-3 model…………………50
Fig. 46 Output spectrum when divide-by-1536……………51
Fig. 47 Output spectrum when divide-by-1575……………51
Fig. 48 The spectrum of the reference oscillator……52
Fig. 49 fdiv is higher than fref ,Vctrl is pulled down to 0V…………53
Fig. 50 fdiv is lower than fref, Vctrl is pulled up to 1.5V………………54
Fig. 51 Loop diagram with external VCO…………………56

REFERENCE

[1] Derek K. Shaeffer, Stanford University, Thomas H. Lee, Stanford University, “The Design and implementation of low-power CMOS radio receivers” KLUWER ACADEMIC PUBLISHERS

[2] Farbod Behbahani, Member, IEEE, Hamid Firouzkouhi, Member, IEEE, Ramesh Chokkalingam, Siamak Delshadpour, Alireza Kheirkhahi, Mohammad Nariman, Student Member, IEEE, Matteo Conta, and Saket Bhatia “A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002

[3] Giampiero Montagna, Giuseppe Gramegna, Ivan Bietti, Massimo Franciotta, Member, IEEE, Andrea Baschirotto, Senior Member, IEEE, Placido De Vita, Roberto Pelleriti, Mario Paparo, Member, IEEE, and Rinaldo Castello, Fellow, IEEE “A 35-mW Fully Integrated 0.18-um CMOS GPS Radio”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, JULY 2003

[4] Valence Semiconductor , Inc. VS7001 “A GPS front end downconverter” JAN 2002

[5] Hamid R. Rategh, Tavanza, Inc., Thomas H. Lee, Stanford University, “ Multi-GHz frequency synthesis & division, Frequency synthesizer design for 5GHz wireless LAN systems”

[6] Ali Hajimiri, Thomas H. Lee, Center for Integrated Systems, Stanford, CA 94305-4070, USA “Phase noise in CMOS differential LC oscillators”, IEEE 1998

[7] D. B. Leeson, “A simple model of feedback oscillator noise spectrum”, Proc. IEEE, pp. 329-330, Feb. 1966.

[8] F. M. Gardner, “Phase lock Techniques”, New York, NY: John Wiley & Sons, 1979.