臺灣博碩士論文加值系統

由於對於動態隨機存取記憶體(DRAM)容量的需求有隨著時間而倍增的趨勢，如何在有限的面積與現有的製程技術之下製作出高容量的DRAM，是一項亟需克服的問題。而多級動態隨機存取記憶體(Multilevel DRAM)的架構，是在一個記憶體單元(Unit Memory Cell)裡存放兩個甚至多個位元(Bit)。與以往一個記憶體單元只存放一個位元的DRAM架構比較，多級動態隨機存取記憶體不但可以解決在有限面積裡倍增記憶容量的問題，也可以在現有的製程技術之下採用較合理的設計方式來進行製作而節省設計與生產成本，並獲得較佳的產率與良率。
在此論文中，我們提出了一個新的多級動態隨機存取記憶體架構，以及這一個架構在讀取、寫入資料時的詳細動作描述。並且將這一個新的架構與以往所提出的多級動態隨機存取記憶體架構以SPICE的電路模擬方式來進行比較。另外由於低功率與低電壓為現今電路設計所需考慮的重點之一，在論文裡面也將對這一個新的架構在因應此潮流之下而採用的技術做一些介紹，以及其成效的展現。

Since raising the density of DRAM by reducing the physical size of cells and using finer design rules becomes increasingly expansive and more difficult, multilevel DRAM technology, which records more than one bit in each memory cell unit, becomes an important way for adopting to increase DRAM density.
In this Thesis, a new multilevel DRAM structure with its storing and retrieving operations is described. SPICE simulations for the new structure and other proposed multilevel DRAM schemes are given to compare them directly. Besides, the new structure could work without boost circuits, which reduces much power consumption and makes it be suitable in the low-power, low-voltage trends.

CHAPTER 1. INTRODUCTION TO MULTILEVEL DRAM
1.1 Concepts of Conventional DRAM Storage
1.2 Concepts of Multilevel DRAM Storage
1.3 Purposes of Research in Multilevel DRAM Storage
CHAPTER 2. REVIEW OF MULTILEVEL DRAMS
2.1 Furuyama''s Multilevel DRAM
2.1.1 Read Operation
2.1.2 Write/Restore Operation
2.1.3 Advantages/Disadvantages of the Design
2.2 Gillingham''s Multilevel DRAM
2.2.1 Read Operation
2.2.2 Write/Restore Operation
2.2.3 Advantages/Disadvantages of the Design
2.3 Okuda''s Multilevel DRAM
2.3.1 Read Operation
2.3.2 Write/Restore Operation
2.3.3 Advantages/Disadvantages of the design
CHAPTER 3. INTRODUCTION TO OUR NEW MULTILEVEL DRAM
3.1 A New Multilevel DRAM structure
3.2 Read Operation
3.3 Write/Restore Operation
3.4 Discussion of the New Multilevel DRAM
CHAPTER 4. SIMULATION AND COMPARISON
4.1 Simulation Environment Setup
4.2 Simulation Results
4.3 Results Comparison
CHAPTER 5. POWER CONSIDERATION
5.1 Approaches of Reducing Power Consumption
5.2 Power Reduction in Multilevel DRAMs
5.3 Elimination of Boost Circuits in our Scheme
5.4 Increasing Sensitivity of Sense Amplifiers
5.4.1 Method 1 of DVt Compensation Circuit
5.4.2 Method 2 of DVt Compensation Circuit
5.4.3 Summary
CHAPTER 6. Conclusion
6.1 Properties of our New Multilevel DRAM
6.2 Future work
REFERENCES

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