臺灣博碩士論文加值系統

資訊科技發展一日千里，為使電腦速度更快、容量更大，因此速度更快、容量更大的記憶體亦為現今發展的方向。現今市場佔有率最高的記憶體為動態隨機存取記憶體（Dynamic Random Access Memory，簡稱DRAM），原因在於其體積小亦可製於IC。但由於動態隨機存取記憶體是以電容為資料儲存裝置，因此其存取的速度較慢，改進動態隨機存取記憶體速度的研究一直持續在進行。本篇論文針對改善動態隨機存取記憶體速度的方向研究，並應用同步動態隨機存取記憶體（Synchronous DRAM ，簡稱SDRAM）的概念，使動態隨機存取記憶體速度提升。
我們研究的方向是期望在一次的運作當中，同時在儲存單元陣列(Cell array)中選擇一個以上的儲存單元(Memory cell)，同時做一個以上的資料的寫入或讀取。大量的資料可同時寫入或讀取，則動態隨機存取記憶體的速度可加快許多。
本篇論文的研究是利用串列輸入-並列輸出的暫存器（Series-input Parallel-output Register），使兩組位址可同時傳輸至記憶體陣列中，選擇兩個記憶體單元作讀取或寫入的動作。在記憶體儲存單元一次充放電的時間內，我們設計此電路同時做兩個記憶體儲存單元的動作，故速度比傳統的一次只對一個儲存單元動作，可大約增加二倍；未來的發展可繼續朝更多記憶體儲存單元同時動作的方向研究，將可提昇更多速度。

With the development of computer technology, the faster and larger quantity memory is required for improving computer efficiency. The Dynamic Random Access Memory (DRAM) is the highest volume production in the memory market because of the small size. However, the speed of DRAM is slow because of the storage device, capacitor. In recent years, many papers adapt to use various methods to improve the damage of the speed of DRAM. Our studying discusses the data rate improvement of dynamic random access memory. In order to increase the access rate of DRAM, we try to use the Synchronous Dynamic Random Access Memory (SDRAM) architecture to obtain our purpose.
Our research tries to realize the architecture that can choose more than one cells in cell array in one access time. We choose more than one cells to do the operation of reading or writing at the same time. DRAM’s access data rate increases when large amount of cells can be read or written in one access time.
In this article, we use the series-input parallel-output register to transport two addresses to memory array. The two addresses choose two storage cells to do the operation of reading or writing. The circuit can implement the operations of reading or writing of the two storage cells at one access time. Therefore, the speed of the new SDRAM architecture is nearly twice as fast as the traditional DRAM. In the future, we can try to choose more than two storage cells to do the operation at one access time, and as a result the speed of SDRAM will get higher.

第一章 簡介................................1
1.1 動態隨機存取記憶體之介紹............1
1.2 同步動態隨機存取記憶體之介紹........8
第二章 同步動態隨機存取記憶體之設計........12
2.1 暫存器之設計.......................18
2.2 解碼器與或閘之設計.................24
2.3 感測放大器之設計...................35
2.4 資料輸入端之設計...................41
第三章 訊號產生器之設計....................43
3.1 壓控振盪器之設計...................44
3.2 訊號產生器之設計...................54
第四章 結論................................61
參考文獻...................................64

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