臺灣博碩士論文加值系統

摘要

本論文以USB2.0規範作為探討高速傳輸技術之藍本，並進一步採用TSMC 0.18um CMOS 1P5M的製程條件及參數來完成USB2.0實體層類比前端接收器的設計。
文中將首先介紹應用於高速傳輸的電路結構及技術。同時，我們提出了符合 USB2.0 規範可向下相容USB1.1的實體層類比介面相對應的電路設計，內容包含了高速差動資料接收器、傳輸封包偵測器、裝置斷開封包偵測器、全速/低速共用之差動資料接收器，最後為兩個分別對應到匯流排通道(+)及匯流排通道(�{)的單端資料接收器。其中高速差動資料接收器負責480Mbps高速傳輸訊號接收的角色， 傳輸封包偵測器則必須可判斷分辨有效的高速訊號及雜訊，裝置斷開封包偵測器則須能察覺裝置實體是否斷開連線; 全速/低速共用之差動資料接收器負責12Mbps全速及1.5Mbps低速傳輸訊號接收的角色;單端資料接收器則可各別的接收匯流排通道(+)及匯流排通道(�{)上流通之訊號。資料匯流排的訊號經由這五個部分的電路處理後將傳送到數位電路作下一流程之處理，而為了節省電源，電路分別設有致能電路，可由數位電路決定各電路的操作時機。
在整個設計過程中，我們主要利用 HSPICE模擬軟體工具搭配 TSMC 0.18um CMOS 元件模型來進行電路的模擬及分析。　

ABSTRACT

This thesis is to discuss the high-speed transmission technique under the USB2.0 (Universal Serial Bus Revision 2.0) specification compliant, and to implement the circuit design of USB2.0 physical layer analog front-end receiver by using the process and SPICE models of TSMC 0.18um CMOS 1P5M.
In the content, several frequently used circuit structures and techniques are introduced for high-speed transmission. In addition, a physical layer analog front-end receiver circuit design for USB2.0 that is backward compatible with USB1.1 is proposed. The design is composed of the high speed differential data receiver, the transmission envelope detector, the disconnection envelope detector, the full/low speed differential data receiver and two single-ended receivers for data bus (+) and data bus (�{). The role of the high speed differential data receiver is to receive high-speed signal with a data rate of 480Mbps. The transmission envelope detector has to sense and distinguish between high-speed signal and noise from the data bus. The disconnection envelope detector has to detect the state of connection between two devices. The full /low speed differential data receiver is for receiving the signal of full speed with a data rate of 12Mbps and low speed with a data rate of 1.5Mbps. The last are two single-ended receivers that are for receiving the signal from data bus (+) and data bus (�{), respectively. The signals on the data bus are processed by the circuits mentioned above to produce the outputs to the digital circuit. Then, the digital circuit decides the data flows of these outputs of the receivers. To save the power, a power down control circuit (PD) is added at each block.
HSPICE is used to verify the overall circuit, and simulated by using the SPICE models of TSMC 0.18um CMOS 1P5M process.

CONTENTS
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 The USB2.0 Overview 2
1.2.1 Goals for the Universal Serial Bus 2
1.2.2 Taxonomy of Application Space 2
1.2.3 Feature List 4
1.3 Organization of the Thesis 5
CHAPTER 2 THE ARCHITECTURAL OVERVIEW OF USB2.0 6
2.1 USB System Description 6
2.1.1 Bus Topology 7
2.1.2 USB Host 8
2.1.3 USB Devices 8
2.2 Physical Interface 10
2.3 Bus Protocol 12
2.4 Robustness 13
2.5 System Configuration 13
2.5.1 Attachment of USB Devices 13
2.5.2 Removal of USB Devices 14
2.5.3 Bus Enumeration 14
2.5.4 USB Host: Hardware and Software 14
2.6 Data Encoding/Decoding 15
2.6.1 NRZI Data Encoding 15
2.6.1 Bit Stuffing 16
CHAPTER 3 THE BUILING BLOCKS OF THE RECEIVER 17
3.1 The Schmitt Triggers 17
3.1.1 The Voltage Mode Schmitt Trigger 19
3.1.2 The Current-Mode Schmitt Trigger 24
3.2 One-Shot Pulse Generator 31
3.3 Operational Amplifier 35
3.3.1 Two-Stage Operational Amplifier 36
3.3.2 Operational Amplifier with Rail-To-Rail Input Common-Mode Range 37
CHAPTER 4 CIRCUIT IMPLEMENTATION AND SIMULATION 43
4.1 Transmission Envelope Detector 45
4.2 High Speed Differential Data Receiver 50
4.3 Disconnection Envelope Detector 55
4.4 Full Speed/Low Speed Differential Data Receiver 58
4.5 Single-Ended Receiver 61
4.6 Summary 64
4.6.1 High-Speed Mode 64
4.6.2 Full-Speed Mode 68
4.6.3 Low-Speed Mode 71
4.6.4 The Test Configuration 73
CHAPTER 5 CONCLUSIONS 75
REFERENCES 78

REFERENCES
[1] “Universal serial bus specification, Revision 2.0,” April 27, 2000
[2] J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital integrated circuit: A design perspective, Second edition, Prentice Hall, 2003.
[3] R. J. Baker, H. W. Li and D. E. Boyce, CMOS circuit design, layout, and simulation. New York, IEEE PRESS, 1998.
[4] Z.Wang, and W. Guggenbuhl, “Novel CMOS current Schmitt trigger,” Electron. Lett., pp. 1514-1516, Nov 1988.
[5] Z. Wang, “CMOS current Schmitt trigger with fully adjustable hysteresis,” Electron. Lett., Vol.25, No.6, pp.397-398, March 1989.
[6] B. Razavi, Design of analog CMOS integrated circuits, New York, Mc Graw Hill, 2001.
[7] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Second edition, Oxford, 2002.
[8] R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. Huijsing, “A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,” IEEE J. Solid-State Circuits, vol.29, no.12, pp.1505–1513, Dec. 1994.
[9] J. J. Nam, Y. J. Kim, K. H. Choi, H. J. Park, “A utmi-compatible physical-layer USB2.0 transceiver chip,” in Proc. IEEE SOC Conference, 2003, pp. 309- 312, Sept. 2003.
[10] J. J. Nam, Y. J. Kim H. J. Park, “A USB2.0 analog front-end design including output drivers and a transmission envelope detector,” in Proc. DEC Conference 2003-summer.