臺灣博碩士論文加值系統

在一個收發機系統裡，PLL是一個重要且不可缺少的一個部分，PLL包含了頻率相位偵測器、充電幫浦、迴路濾波器、壓控振盪器、除頻器，除了追求效能外，低功耗，低相位雜訊，較寬的工作頻率範圍都是我們所注重的目標，其中又以壓控振盪器和除頻器特性最重要。
首先，第一部分我們提出一個超寬頻注入鎖定除3除頻器，此除頻器使用台積電0.18微米製程，晶片面積為0.803 × 0.851 mm2。此篇論文使用了雙注入的MOSFETs及共振腔，設計出一個好的被動共振腔是獲得超寬頻除頻範圍的關鍵。工作電壓操作在0.76伏特，整體功耗為7.77 mW，在注入強度為0 dBm時，除頻範圍可從8.4 GHz~13.5 GHz，百分比為46.58 %。
接著，我們呈現一個利用單端注入的注入鎖定除3除頻器。其使用台積電0.18微米製程，晶片面積為0.803 × 0.851 mm2。此篇論文使用了兩種觀念，一是線性混波器，另一個則是利用了一組可以有效降低品質因素(Q-factor)的LC共振腔，來達到超寬操作範圍與除頻範圍。工作電壓操作在0.76伏特，整體功耗為7.97 mW，在注入強度為0 dBm時，除頻範圍從10.28GHz~13.25GHz，百分比為25.25 %。操作範圍為8.08~13.25 GHz，百分比為48.5 %
最後，我們呈現一個注入鎖定除2除頻器，使用的是一個雙頻RLC共振腔。其使用台積電0.18微米製程，晶片面積為0.785×0.883 mm2。此篇論文使用了一組LC震盪器並同時讓LC震盪器並聯電路下方的交叉耦合以補償LC震盪器的損耗。於兩個可變電容連接處加上電阻，使其增加電路的除頻範圍。工作電壓操作在0.8伏特，整體功耗5.57 mW，在注入強度為0 dBm時，除頻範圍從2.2 GHz~9.1 GHz，百分比為122.12 %。

In a RF transceiver system, PLL is a part not only important but also indispensable, PLL include Phase Frequency Detector (PFD),Charge Pump (CP),Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD),low-power, low phase noise, wide operating frequency range are what we focus on , and they are the most important performance of the VCO and Divider.
First, we proposes an ultra-wide-locking-range CMOS divide-by-3 injection-locked frequency dividers (ILFD). The fabricated 0.18 μm CMOS ÷3 ILFD uses cross-coupled switching transistors, direct-injection dual-injection MOSFETs and a resonator. Proper design of passive resonator is the key to obtain an ultra large locking range. The consumed power of the ÷3 ILFD core is 7.77 mW at the dc drain-source voltage of 0.76 V. The measured single-band locking range percentage is 46.58% at the injection power of 0 dBm.
Secondly, a wide-locking-range CMOS divide-by-3 injection-locked frequency dividers (ILFD) using single-ended injection signal is presented. The fabricated 0.18 μm CMOS ÷3 ILFD uses cross-coupled switching transistors, single injection MOSFET and a dual-resonance RLC resonator. We use both the concept of linear mixer and Q-factor degraded LC resonator. These two concepts are used to enhance the operation range and locking range. At an external injected signal power Pinj = 0 dBm, the measured locking range is 2.97 GHz (25.25%) from 10.28 to 13.25 GHz and the operation range is 5.17 GHz (48.5%) from 8.08 to 13.25 GHz. The die area is 0.803 × 0.851 mm2. The consumed power of the ÷3 ILFD core is 7.97 mW
Finally, a wide locking range divide-by-2 RLC injection-locked frequency divider (ILFD) is designed and implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD is based on a cross-coupled oscillator with two direct injection MOSFETs in series and a dual-resonance RLC resonator. The resonator is used to enhance the locking range. At the drain-source bias of 0.8 V ranging and at the incident power of 0 dBm ,the locking range of the divide-by-2 ILFD is 6.9 GHz, from the incident frequency 2.2 to 9.1 GHz and the locking range percentage is 122.12 %. The power consumption of ILFD core is 5.57 mW. The die area is 0.785 × 0.883 mm2.

中文摘要 I
Abstract III
Table of Contents VI
List of Figures VIII
List of Tables XII
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 5
Chapter 2 Overview of Oscillators 7
2.1 Introduction 7
2.2 Basic Theory of Oscillators 9
2.2.1 One-Port (Negative Resistance) View 10
2.2.2 Two-Port (Feedback) View 14
2.3 Classification of Oscillator 16
2.3.1 LC-Tank Oscillators 16
2.3.2 Resonatorless Oscillators 19
2.4 Parallel RLC Tank 21
2.4.1 Design of Inductor 22
2.4.2 Inductor’s Quality Factor 26
2.4.3 Design of Transformer 31
2.4.4 Design of Resistors 39
2.4.5 Design of Capacitors 40
2.4.6 Design of MOSFET Varactors 42
2.5 Design Concepts of VCOs 47
2.5.1 VCO Characteristic Parameters 48
2.5.2 Phase Noise in Oscillators 50
2.5.3 Quality Factor 58
2.5.4 Pulling in Oscillators 61
2.5.5 Tail Current Source 64
Chapter 3 Overviews of Injection Locked Frequency Divider 66
3.1 Introduction 66
3.2 Operation Principle 67
3.1.1 Locking Range 68
3.1.2 Example For A Single Injection Of ILFD 71
Chapter 4 A Wide-Locking Range and Operation Range Divide-by-3
Injection-Locked Frequency Divider With Quality-Factor Degraded LC Resonator 73
4.1 Introduction 73
4.2 Circuit Design 75
4.3 Measurement Result 81
Chapter 5 Wide-Locking Range Single-Injection Divide-by-3 Injection-Locked Frequency Divider 88
5.1 Introduction 88
5.2 Circuit Design 89
5.3 Measurement Result 91
Chapter 6 Divide-by-2 Injection-Locked Frequency Divider Using Dual-Resonance RLC Resonator 96
6.1 Introduction 96
6.2 Circuit Design 98
6.3 Measurement Result 104
Chapter 7 Conclusion 109
References 111

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