臺灣博碩士論文加值系統

本論文研究藉由UV奈米壓印微影技術配合傳統薄膜電晶體製程，製作多重奈米通道薄膜電晶體，我們已成功使用電子束微影的製作出最小線寬與間距為200nm/100nm，高度約350nm的高深寬比HSQ壓印模具，並運用於UV奈米壓印在多晶矽上製作出最小線寬/間距約為100nm/200nm的奈米多通道結構，成功製作出之奈米多通道薄膜電晶體。
此外藉由HP-4156及HP-4284量測完成的元件來了解多通道結構的改變對於元件的操作特性，由實驗結果發現，線寬100 nm/間距200 nm的奈米多通道結構薄膜電晶體，展現出較其他不同線寬與間距的多晶矽薄膜電晶體，有較高開關電流比(8.12XE6)，較低的臨界電壓(0.9V)，載子遷移率為(37.2 cm2/V-s )，及更為陡峭的次臨界擺幅(0.437 V/dec)，未來將可運用在平面顯視器之薄膜電晶體上

In this thesis, the multiple nano-channel thin film transistors were fabricated by combing the UV nano imprint technology and the traditional thin film transistor process. The HSQ nano mold, with the minimum line/spacing width of 200nm/100nm and the maximum height of 350nm, was fabricated by E-Beam lithography. The Poly-Si multiple nano-channels were fabricated by UV nanoimprint and reactive ion etching. Then the thin film transistors were fabricated by following the conventional TFT process.
The electrical characterizations of multiple nano-channel TFTs were measured by HP4156 and HP4284. In our results, the multiple nano-channel TFTs with the line the minimum line/spacing width of 200nm/100nm, show the best on-off current ratio (8.12XE6), the threshold voltage (0.9V), the carrier mobility of (37.2 cm2/V-s ), and the subthreshold swing (0.437 V / dec) in all devices. This technique will be suitable for the future TFTs on the flat panel display.

中文摘要 Ⅰ
英文摘要 Ⅱ
誌謝 Ⅲ
目錄 Ⅳ
圖目錄 Ⅶ
表目錄

第一章 序論
1-1 研究動機
1-2 論文架構
第二章 理論基礎
2-1 薄膜電晶體簡介
2-1-1 FinFET元件介紹
2-1-2 多通道薄膜電晶體介紹
2-1-2 SONOS記憶體元件介紹
2-2 奈米壓印技術介紹
2-2-1 熱壓式微影技術
2-2-2 UV奈米壓印微影
2-2-3 微接觸轉印技術
2-2-4 壓印模具的製作方式
2-2-5 HSQ材料簡介
2-2-6 脫模劑介紹
第三章 實驗方法與流程
3-1 薄膜電晶體製作流程
3-1-1 多重奈米通道薄膜電晶體製作流程
3-1-2 SONOS記憶體製作流程
3-1-3元件光罩設計與結構說明
3-2 壓印模具的製備
3-2-1 奈米壓印HSQ模具設計及製作
3-2-2 HSQ模具曝光及顯影
3-2-3 脫膜劑的使用
3-3 奈米多通道結構製作實驗
3-3-1 UV奈米壓印實驗
3-3-2 殘留層蝕刻實驗
3-3-3 多晶矽蝕刻實驗
3-4 奈米多通道後黃光微影蝕刻製程實驗
3-4-1 主動區圖形定義
3-4-2 閘極圖形定義
3-4-3 接觸窗圖形定義
3-4-4 鋁電極圖形定義
3-5 電性參數萃取
3-5-1 臨界電壓定義
3-5-2 次臨界擺幅定義
3-5-3 開關電流比定義
3-5-4 載子移動率定義
3-5-5 記憶體寫入操作原理
3-5-6 記憶體抹除操作原理
第四章　實驗結果與討論
4-1 HSQ模具顯影結果分析
4-2 UV奈米壓印結果分析
4-2-1 多通道結構壓印分析
4-2-2 殘留層去除
4-2-3 多通道結構蝕刻結果
4-3 主動區定義
4-4 閘極定義
4-5 接觸窗定義
4-6 鋁電極定義
4-7 元件量測結果分析
4-7-1 單通道與多通道線寬200nm間距600nm電性比較
4-7-2 奈米通道通道長度(10um)不同線寬相同間距相同電性較
4-7-3 奈米通道通道長度(5um)不同線寬相同間距相同電性比較
4-7-4 多通道相同線寬間距不同蝕刻時間比較

第五章 結論
引用文獻

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